Thursday, 2019-02-07

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promach_ZipCPU: Hmm... , I am really not sure why cover(in_valid); failed10:50
promach_I have played around those lines with reference to in_valid10:50
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finnbHi - I'm planning on starting a project at work with a few colleagues. We want to be able to work on several different projects which share common components in the same repo. I'm trying to get an idea for a good project layout. Has anyone got any expamles?11:06
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ZipCPUfinnb: You mean ... how to organize your files?12:03
ZipCPUI might recommend each major component and each major get its own git repository.  That way you can specifically include updates to your systems from component repositories in a managed fashion.12:05
ZipCPUi.e. nothing changes without a "git pull" on the component repository.  (See git submodules for how to do this)12:05
ZipCPUOf the repositories I've seen, however, the solution(s) have been mixed.  Not everyone does it this way.  Some repos, such as the USRP repos, have a directory for common components and another directory for the various top level designs the components are used to build12:06
ZipCPUpromach_: First two steps to dealing with any bug 1) add `default_nettype none, and 2) Make sure your design passes a verilator -Wall -cc multiply.v # check12:10
ZipCPUThe more modern Verilator versions should be able to handle your formal stuffs to, so you might wish to try: verilator -Wall -DFORMAL -cc multiply.v12:10
keesjfinnb: it used to be hard for people to collaborate but I think in 2019 it is safe to say that distributed versioning systems (git) pretty much solved this problem. Work separately in you on repo, when you are done rebase and create nice logical commits. that apply to the master branch. just avoid makefile that have different components on a single line. that is the defacto. now you are talking about using a13:01
keesjshared common components. ... if those are ready/tested/finished there is of course no problem but if they are still in develpoment.. treat them first like local comonents at the end of the project pick the good ones/spend the time merging13:01
keesjs/comonents/components/g all the difficulties you might get from using shared components (even with git submodules) are IMHO not worth the effort and creating the "base of common components" is also some kind of utopia. let the fitest of the survival survive13:04
finnbadding a bit of CI to make sure master is always fine isn't my problem13:05
finnbMy problem is more... dependency management13:05
keesjit is more complex .. it is not because it is in master that it will apply/work on your local branch. of course some CI is great but that won't guard you against API changes and there you come to work on monday morning half way into solving a nice problem and you end up with a broken dependency because somebody had a different idea on how master should work.13:07
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keesjI tried (not on VHDL/verilog) I must say many times but I find that the result are bulky systems that need to work in all previous and future edge cases. Creating a repo for shared code is I guess not that bad but deciding when to fetch code is a strategy that one can choose.13:10
keesjif you work locally (and use git) you are always free to pull and attempt a git rebase master. if it works .. great13:11
keesjthere are a few possibilities described here to share code / release code and remain sane
tpbTitle: Gitflow Workflow | Atlassian Git Tutorial (at
finnbI made a tool a while ago, albeit a very bad one, in which you listed the dependencies of a file. For example infra/fifo.v depends on infra/mem.v. Then if projects/foo/bar.v dpeneded on infra/fifo.v, it was fine because I had a yml file which would have a cfg file for bar.v which said it had a dependency on infra/fifo.v13:12
finnbI just wondered if there was anything like this out there alredy13:12
finnbs/I had a yml file which would have a cfg file/I had a cfg file13:13
finnbAnd it would generate the correct makefile for yosys / pnr / icestorm13:14
finnbVersion controlling I have dealt with on bigger projects. This is just a team of 3 people. We won't be making API changes. I'd just like a way of controlling verilog dependencies13:14
keesj(with ghdl the same exists e.g but a bit more easy. you compile once using compile */*.v and then generate a makefile) don't know about yosys. but makefiles are often .. hell :P13:17
keesjvunit follows a similar approach
tpbTitle: User Guide VUnit documentation (at
keesj(avoiding the makefiles in the first place)13:19
finnbI spotted a yosys -E flag earlier which I have yet to try out13:26
keesjomg.. I rembered my solution ... differently but.. it was an ugly shell script it worked and I did not think further
tpbTitle: can-hdl/ at master · keesj/can-hdl · GitHub (at
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ZipCPUfinnb: Are you familiar with FuseSoC?14:41
ZipCPUFuseSoC was designed to be / intended to be a configuration manager for FPGA designs composed of multiple parts from multiple separate distributions14:58
ZipCPUFeel free to ask about it on gitters #libresoc/fusesoc channel.  You'll find olofk there.  He should be able to help you get started15:00
ZipCPUI haven't tried it myself yet15:00
keesj also show "icosoc" that also looks nice (for ice40 boards) . I am currently learning migem/litex15:11
finnbThanks :)15:12
finnbI'll likely be just targetting the ulx3s board for now anyway15:12
finnbThanks for your help though and I will certainly look into this15:13
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promach_ZipCPU: I really hate c++ coding during verilator usage16:44
ZipCPUIt must really be a struggle to have so much hatred within yourself16:44
promach_I am not sure why all the commercial simulators in does not work with 3D array in systemverilog16:45
ZipCPUVery few tools support multidimensional arrays.  This is probably due to the fact that few (if any) hardware implementations support it16:46
finnbiverilog + gtkwave does :)16:46
ZipCPUYou might wish to check your implementation against the standard, though --- I'm not sure that's how to implement a 3D array16:47
finnbI need to get into verilator16:50
finnbI'm still a "let's look at the waveform" kinda guy16:50
ZipCPUVerilator will support the "let's look at a waveform" philosophy16:52
promach_ZipCPU: I know what went wrong16:52
ZipCPUGlad I could help.  You might want to thank finnb for his help as well.  ;)16:52
promach_thank finnb16:52
finnbno problem haha16:53
promach_strange, reg [(NUM_OF_INTERMEDIATE_LAYERS-1):0][0:(SMALLER_WIDTH-1)][(A_WIDTH+B_WIDTH-1):0] middle_layers; works in Cadence, but not in iverilog16:55
promach_iverilog systemverilog support is still ongoing16:56
promach_the code also has no problem with vcs16:56
promach_finnb : same problem with yosys-smtbmc16:57
finnbhmm sorry you're hitting the limit of my knowledge here16:59
finnbSo you've tried the dumpvars function?16:59
finnbI think it's $dumpvars(0, filename)17:00
tpbTitle: multiply.v(1) - EDA Playground (at
finnbok I have one thing you can try17:01
finnbHave you tried using a generate statement?17:02
promach_for what ?17:02
finnboh wait a sec17:02
finnb$dumpvars(0, test_multiply);17:02
promach_and ?17:03
finnbIs that the only place you dumpvars?17:03
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finnbAnd your problem is you want to dump a 3d array?17:03
finnbYeah ok I have dumped a 2D array with the following method as iverilog doesn't do it by default17:04
promach_the problem does not exist in vcs or cadence17:04
promach_but the problem exist in iverilog17:04
tpbTitle: [VeriLog] integer k; initial begin $dumpfile("./bu - (at
finnbTry adding something like this17:05
finnbIt will puke up a load of warnings but just ignore them17:05
finnbyou can adapt this to a 3d array I imagine17:05
finnbThough I haven't tried17:05
finnbhave you tried that17:06
finnbchange the filename to the filename you're using obviously17:06
promach_no the problem is that the same testbench works with cadence and vcs17:06
promach_but not iverilog17:06
promach_do you get it ?17:06
promach_and yosys-smtbmc seems to have issue with 3D array too, please correct me if wrong17:07
finnbNot really sorry, I thought your original problem was with 3d arrays and you wanted a workaround17:07
promach_I should not say testbench, testbench is okay as far as I can see now17:08
promach_I would say the souce code itself17:08
finnbSo is your 3d array issue only in simulation or does it also not build?17:09
promach_finnb : click the run button17:09
promach_using cadence, vcs or iverilog17:09
promach_then you will find that only iverilog gives you error17:10
finnbThat requires me to create an account17:10
promach_I mean the run button within
tpbTitle: multiply.v(1) - EDA Playground (at
promach_a corporate company or educational institute email account will do17:11
finnbCan you paste in the error message instead? I'm neither corporate or in education17:13
* promach_ had a preliminary conclusion that both iverilog and yosys-smtbmc do not support reg [(NUM_OF_INTERMEDIATE_LAYERS-1):0][0:(SMALLER_WIDTH-1)][(A_WIDTH+B_WIDTH-1):0] middle_layers;17:13
promach_multiply.v:96: error: A reference to a wire or reg (`pp_index') is not allowed in a constant expression.17:17
promach_multiply.v:96: error: Array index expressions must be constant here.17:17
promach_multiply.v:97: error: A reference to a wire or reg (`pp_index') is not allowed in a constant expression.17:17
promach_multiply.v:97: error: Array index expressions must be constant here.17:17
promach_I guess a normal gmail account is suffice to use iverilog in edaplayground17:18
promach_only commercial simulators need a corporate company or educational institute email account17:18
promach_finnb: it is a bit late here. Shall we discuss later ?17:20
promach_or you can leave message here. I will be back later17:20
somlodaveshah: ping17:22
finnbpromach_, I have an idea17:23
finnbJust humour me and try this17:24
finnb reg [(NUM_OF_INTERMEDIATE_LAYERS-1):0] middle_layers [0:(SMALLER_WIDTH-1)] [(A_WIDTH+B_WIDTH-1):0];17:24
finnbI'm actually just cooking17:24
finnbIt isn't so late for me :P17:24
finnbHmm actually I think your error is elsewhere tbh17:25
finnbI just get this:  reg [(NUM_OF_INTERMEDIATE_LAYERS-1):0] middle_layers [0:(SMALLER_WIDTH-1)] [(A_WIDTH+B_WIDTH-1):0];17:28
finnbI just get some tomcat error17:28
somlodaveshah: I'm trying to modify the soc_versa5g pll.v example to give me 10MHz by changing s/CLKI_DIV(2)/CLKI_DIV(10)/17:33
tpbTitle: Imgur: The magic of the Internet (at
somlodaveshah: and wondering if I have to change any other parameters (not quite sure what the other *_DIV parameters are for), before I re-run synthesis, which takes several hours :)17:37
daveshahsomlo: iirc there is a minimum input frequency after the divider, on phone rn so can't easily check but be careful with that17:38
daveshahIs synthesis really that slow? Where is it getting stuck?17:38
somlodaveshah: not getting stuck, just lots of work to do (rv64imadc rocket chip bare-metal demo -- inspired by soc_versa5g)17:42
somlonot enough room for "f", even on the 85k ECP5 :) but the f-less version fits on the 45k; nextpnr says it can go up to 10MHz17:43
daveshahOh awesome17:43
somloI wanted it to *actually* work before posting the code, but that rarely works out for me in real life :D17:44
daveshah should speed up placement by around an order of magnitude, but routing still needs a bit more work to speed up17:44
tpbTitle: [EARLY WIP] HeAP-based analytical placer by daveshah1 · Pull Request #219 · YosysHQ/nextpnr · GitHub (at
somloso I think I might have screwed up the reset signal generator, and wanted to double-check the clock signal is OK before waiting another 4 hours to see if it worked17:45
daveshahThe ecppll tool should give a working config17:46
MoeIcenowy somlo: how did you deal with rocketchip?17:47
somlooh, cool, I'll see if I can figure out how to use it; Will also test-drive the pull request you referenced17:47
MoeIcenowyI'm afraid of the unreadable sources dumped by chisel17:48
somloMoeIcenowy: I'll throw it up on github later today, either as a patch to prjtrellis (another demo folder in "examples") or as its own repo for the full details17:48
somlobut short version: I use sed to add uart and led signals to the top-level test harnes all the way through to the "external" mmio behav_sram module17:49
somloit's mostly makefile magic :)17:49
MoeIcenowyBTW the VQM output functionality of Yosys seems to be broken when dealing with BRAM17:50
somloand I replaced the mmio and RAM "behav_srams" with my own implementations: small(er) RAM initialized to "firmware.hex", and the MMIO one that twiddles the leds and uart17:50
MoeIcenowysmolo: BTW what's the LUT input number of ECP5?17:59
MoeIcenowy4 or 6?17:59
somloI *think* 418:00
MoeIcenowyoh I should read yosys techlib18:01
MoeIcenowyseems to be 4 with muxes inside cell18:01
daveshahYeah, LUT4 with cascade muxes to build up to a LUT7 using an entire tile18:04
MoeIcenowyBTW is LUT4 better or LUT6?18:07
MoeIcenowy(seems a very newbie question)18:07
MoeIcenowy(my own think is that LUT4 is more space cheap but LUT6 has better timing18:07
daveshahI don't think it's a better or worse, but your thinking sounds reasonable18:09
daveshahThe fact Xilinx uses LUT6 makes me think it's best for max performance18:10
daveshahI think I've seen somewhere that LUT4 has lower power18:10
somlodaveshah: ok, here's what I'm building right now:
tpbTitle: GitHub - gsomlo/yoloRISC: porting lowRISC to yosys/nextpnr/trellis on the Lattice ECP5 fpga (at
somloI'll probably nuke it and post a pull request as yet another demo for prjtrellis if/when I get it working :)18:14
somloafter which I'll dedicate myself to understanding "litedram" and finding an 85k board with adequate memory (or trying to bribe someone into redesigning one) :)18:16
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finnbpromach_, I think I may have figured it out21:16
finnbMaybe not21:17
finnbI was going to say, have you checked you aren't initialising any arrays21:17
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daveshahUART doesn't seem working and quite fast because I accidently left SIMULATION defined21:23
daveshahBut this must be one of the most complex blinkies ever21:23
daveshahThanks for your amazing work on this!21:23
daveshahMind if I tweet it?21:23
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