Monday, 2019-02-04

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keesjhttps://fosdem.org/2019/schedule/event/trellis_and_nextpnr/ (video online of daveshah's presentation)09:37
tpbTitle: FOSDEM 2019 - Project Trellis and nextpnr (at fosdem.org)09:37
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shaprZipCPU: students asked if there's a docker image that has all the tools installed18:21
shaprmight be a good thing for your tutorial18:21
ZipCPUshapr: Thanks for the suggestion!18:48
ZipCPUSymbioticEDA routinely creates Vagrant+VirtualBox images with all of the tools installed on them, but these are used when teaching the formal verification course.  Those images come with a 90 day (?) license for the full Symbiotic EDA suite as well.18:49
ZipCPUI've thought about making a docker image, but ... know so little about what would be required to do so that I haven't even tried starting18:49
shaprfair enough18:56
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sxpertZipCPU: care to help a beginner ?19:11
ZipCPUSure, I could use a distraction, what's up?19:12
sxpertI am embarking in this https://github.com/sxpert/hp-saturn/blob/master/saturn_core.v19:12
tpbTitle: hp-saturn/saturn_core.v at master · sxpert/hp-saturn · GitHub (at github.com)19:12
ZipCPUGo on19:13
sxpertwhen I launch the compile script, I don't seem to be getting much back out, what am I missing ?19:13
ZipCPU"compile script"?19:13
sxperthttps://github.com/sxpert/hp-saturn/blob/master/compile19:13
tpbTitle: hp-saturn/compile at master · sxpert/hp-saturn · GitHub (at github.com)19:13
sxpertthis compile script19:13
ZipCPUOk19:14
ZipCPUCan I ask you to make two changes and then come back and ask again?19:14
sxpertsure19:14
ZipCPUChange 1. Add: `default_nettype none // to the top of your source code19:14
ZipCPUChange 2: Run: verilator -Wall -cc saturn_core.v # on your source code19:15
ZipCPUThat will find a lot of bugs in your code.  When verilator -Wall comes back with no more warnings, then let's see what else might be going on.19:15
sxpertok19:15
daveshahsxpert: to get a working ecp5 bitstream, you need to specify both --basecfg and --textcfg to nextpnr19:20
daveshahThen use ecppack on the output from textcfg19:20
daveshahSee https://github.com/SymbiFlow/prjtrellis/blob/master/examples/picorv32_versa5g/Makefile#L1719:20
tpbTitle: prjtrellis/Makefile at master · SymbiFlow/prjtrellis · GitHub (at github.com)19:20
sxpertZipCPU: there are indeed warnings, and even errors19:21
sxpertdaveshah: ah, will look at that19:21
ZipCPUdaveshah: I wasn't expecting that.  Can you explain what's going on?  Why does nextpnr need the extra information, but only for the ECP5?19:21
sxpert(once I have fixed those warnings)19:21
ZipCPUsxpert: Verilator's warnings are fairly easy to fix--especially compared to other tools (Cough Vivado cough cough Quartus)19:21
daveshahZipCPU: because there are a few fixed bits needed for ecp5 bitstreams and I haven't got round to hardcoding them19:22
daveshahbasecfg passes those19:22
ZipCPUSo the basecfg argument is project independent?19:22
daveshahtextcfg is the equivalent of --asc for the ice4019:22
daveshahZipCPU: yes, barring some very odd use cases19:22
sxpertdaveshah: in the example [email protected] is replaced by attosoc_out.config ?19:22
daveshahsxpert: yes19:22
sxpertok19:23
ZipCPUIf textcfg is the equivalent of --asc, why not use --asc instead?19:23
daveshah ZipCPU: because its a different format with a different name19:23
daveshahsxpert: also make sure the textcfg you pass corresponds to the right ecp5 variant19:23
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sxpertdaveshah: ah, looking for one for ULX3S with 85F19:35
sxpertthen19:35
sxpert(which I just received in the mail)19:36
daveshahsxpert: https://github.com/SymbiFlow/prjtrellis/blob/master/misc/basecfgs/empty_lfe5u-85f.config19:36
tpbTitle: prjtrellis/empty_lfe5u-85f.config at master · SymbiFlow/prjtrellis · GitHub (at github.com)19:36
sxpertthanks19:38
sxpertZipCPU: I suppose warnings of the "blah is not used" (because it's not implemented yet) are not a problem19:39
ZipCPUsxpert: Let me show you how to get rid of them ...19:40
ZipCPUAt the bottom of your design, but before the endmodule, insert the following lines:19:40
ZipCPU/ Verilator lint_off UNUSED19:40
ZipCPUwire [N-1:0] unused;19:40
ZipCPUassign unused = { all of your unused nets};19:40
ZipCPU/ Verilator lint_on UNUSED19:40
ZipCPUYou'll need to adjust N to the number of unused wires  you have19:41
ZipCPUThe neat thing about this is that, now when you use some of the bigger tools, they'll warn you about having an unused wire named: unused19:41
ZipCPUYou can then quickly ignore that warning and go onto any others19:41
sxpertZipCPU: I have something wierd line 142, it says RSTK is not used, but it is at various locations19:44
ZipCPUI just searched your design for RSTK19:45
ZipCPUIt appears to be unused19:45
ZipCPUYou reset it to zero, but then do nothing more with it19:45
ZipCPUThere's some code referencing it, but it appears to be commented out19:45
sxpertI do assign things to it on line 78319:46
sxpert(the contents of PC)19:47
* ZipCPU looks19:47
ZipCPUCan you update the github file, so I can see the updates you've made?19:47
sxpertpush done19:48
sxpert(sorry)19:48
* ZipCPU clones hp_saturn19:48
ZipCPULine 873 should have two /'s, not just one--same for line 87619:49
sxpertah, irc ate the first / ;-)19:50
ZipCPUYou'll also need to adjust the N and the {} lines ... since you hadn't done that, I commented the two out19:50
ZipCPUWow, that is one giant state machine19:51
ZipCPUI'm not sure line 306 is right, the case for READ_ROM_STA etc...19:51
ZipCPUSeveral tools have required I use a "begin end" on an empty case19:51
sxpertah19:51
ZipCPULine 438 too19:52
sxpertI can add that no pb19:52
sxpert(there are a bunch of those)19:52
ZipCPUDoes anything reference RSTK?  Or is it set only?19:53
sxpertit will be used when I get to implement the RTN* instructions19:54
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ZipCPUSure, but then it's an unused register19:54
ZipCPUIt's not that it isn't set, it's just unused19:54
daveshahAlso, note the entire design will be optimised away for similar reasons19:55
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sxpertZipCPU: ah, ok, that's what it means19:55
daveshahBecause it has no outputs (other than one that is at a constant value)19:55
sxpertso I should connect say the leds, and show parts of a different register at each clock or something ?19:56
daveshahYes, that would be a good solution19:56
sklvhi, i need an application which does RW on at least 2 sd cards at the same time, drives an oleds102 spi display, and transfers data over an rs232 port - i am trying to estimate whether this is withing my capability to implement with a verilog mcu - are there any examples of a boards where a yosys soft cpu runs code from external flash?19:56
ZipCPUsxpert: Have you seen my logic minimization article?  http://zipcpu.com/blog/2017/06/12/minimizing-luts.html  You might find it valuable19:56
tpbTitle: Minimizing FPGA Resource Utilization (at zipcpu.com)19:56
sklvs/at the same time/not at the same time/19:56
sxpertZipCPU: not yet19:57
ZipCPUsklv: Yes19:57
sklvZipCPU: can you link me please?19:57
sxpertZipCPU: I am trying to get something that works first ^^19:57
ZipCPUIf by "external flash" you mean a flash chip external to the FPGA, then most definitely yes.19:57
sklvthat's what i mean yea, but i want the flash to contain CPU code as opposed to FPGA configuration code19:57
ZipCPUsklv: How about this one, https://github.com/ZipCPU/icozip19:58
tpbTitle: GitHub - ZipCPU/icozip: A ZipCPU demonstration port for the icoboard (at github.com)19:58
ZipCPUOr this one, https://github.com/ZipCPU/s6soc19:58
tpbTitle: GitHub - ZipCPU/s6soc: CMod-S6 SoC (at github.com)19:58
sxpertsklv: it is my understanding you can have both19:58
ZipCPUOr even this one: https://github.com/ZipCPU/openarty19:58
tpbTitle: GitHub - ZipCPU/openarty: An Open Source configuration of the Arty platform (at github.com)19:58
sxpertsklv: depending on the size of said config flash19:58
ZipCPUsxpert: For all the flash work I've done, I have yet to come near to even using a half of the flash19:59
ZipCPUMost flash devices have been plentiful for me19:59
ZipCPUsklv: Most of my designs using flash have used it for both the FPGA configuration as well as for CPU code19:59
sklvthat's fine19:59
sxpertZipCPU: sounds like a perfect fit for my application's rom code19:59
ZipCPUIt can be, but do beware: It will take you many cycles to read from the flash20:00
sxpertZipCPU: plan is to read it all to ram on boot20:00
daveshahHow fast do you need to run at?20:00
ZipCPUHere's a good discussion of how the flash impacts a CPU: http://zipcpu.com/zipcpu/2018/03/21/dblfetch.html20:00
tpbTitle: Pipelining a Prefetch (at zipcpu.com)20:00
sxpertZipCPU: sdram that is20:00
ZipCPUsxpert: My OpenArty design reads from flash into SDRAM on boot20:01
ZipCPUAlthough I discuss it more on this page: http://zipcpu.com/zipcpu/2018/02/12/zbasic-intro.html20:01
tpbTitle: Want to use ZBasic? Let's have some fun--no actual FPGA required! (at zipcpu.com)20:01
sklvZipCPU: so what, artix7 can be handled with an open toolchain now?20:02
sklvi thought it was just lattice20:02
sklvhow new is this just out of interest?20:02
ZipCPUsklv: The differences are irrelevant to the toolchain20:03
sklvoh it says in the repo20:03
ZipCPUsklv: I'm working on a blog entry regarding that repo right now20:03
ZipCPUThe active work has been taking place within the autoarty branch20:03
sklvok, icoboard looks good for my needs - what about anything with a hand solderable fpga so tqfp qfp qfn ?20:04
* ZipCPU shudders at the word "solder" and runs in the other direction20:04
ZipCPU:D20:04
ZipCPUsklv: You might need to ask someone else for soldering advice20:05
daveshahsklv: have a look at the ice40hx4k in the qfp package or the up5k in the qfn package if you don't want bga20:05
daveshahThe former is the same silicon as is on the icoboard20:06
sxpertsklv: ask Louis Rossmann for soldering advice ;)20:07
sklvi don't need soldering advice, i want my fpga in a particular package, although that's been answered anyway :)20:08
* ZipCPU takes a peek to see if it is safe to return to the channel20:08
* sxpert will continue implementing stuff20:10
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