Thursday, 2019-01-31

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keesjFOSDEM anyone?06:53
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sxpertnow that I have tested my module with iverilog, how would I run yosys on it ?11:23
daveshahsxpert: You will want to do something like `yosys -p "synth_ice40 -top top -json design.json" design.v`; `nextpnr-ice40 --up5k --json design.json --pcf design.pcf --asc design.asc`; `icepack design.asc design.bin`11:29
daveshahchanging the name and device type as appropriate11:29
daveshahYou can see an example of a Makefile for this at
tpbTitle: picorv32/Makefile at master · cliffordwolf/picorv32 · GitHub (at
sxpertdaveshah: how do I tell it to ignore the testbench bits ?11:36
daveshahWrap them in `ifdef SIM11:36
daveshahor `ifndef SYNTHESIS11:37
sxpert`ifdef SIM seems to work11:39
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sxperthmm, design is too slow11:47
sxpertneed to add registers in there11:47
sxpertguess I need to add some clocking ;)11:48
sxpertdaveshah: thanks, I have things to work on now ;)11:50
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sxpertdaveshah: hmm, can't figure it out...13:35
sxpertdaveshah: can't get the simulation to show up the clock changing, what am I doing wrong ?
tpbTitle: [VeriLog] module mask_gen ( // ports clk, nibble_width, nibble_start, - (at
daveshahsxpert: try `clk = (clk === 1'b0);` instead of `clk = !clk`13:38
daveshahsorry, `clock = (clock === 1'b0);`13:39
sxpertam getting nothing between "run scheduler13:39
sxpertand "execute StartOfSim callbacks"13:40
daveshahah, you need to pass -DSIM to Icarus13:41
sxpertah !13:41
MoeIcenowyinterestingly... tried iCECube2 recently and found that synplify pro is still LUT efficient than Yosys on my design...13:43
sxpertdaveshah: ah HA !13:46
daveshahMoeIcenowy: yes, that's not too surprising, Yosys isn't brilliantly tuned by any means13:47
daveshah`-relut` might help synth_ice40 a bit13:48
MoeIcenowy(yes it do help a bit13:49
MoeIcenowy(BTW the reason why I'm considering this is because I currently only own a too small iCE4013:49
MoeIcenowyLP384 ;-)13:49
MoeIcenowydaveshah: is the gate->lut process done by ABC?13:49
daveshahwhitequark has been looking at alternative options too13:49
MoeIcenowymaybe I should give -noabc a try?13:51
MoeIcenowyhaha even worse13:51
* sxpert is actually targetting ecp513:51
daveshahThat will be considerably worse, replacing abc with the new `flowmap` command will be better than that but still probably worse than abc13:51
sxpertbut that's ok, I think I got the right options13:51
MoeIcenowydaveshah: by the way it seems that currently it's still not possible for a Linux distro to provide nextpnr w/ prjtrellis?13:52
MoeIcenowy(although I have no ECP513:52
zkmssometimes -relut and/or -abc2 helps, idk13:52
daveshahsxpert: have a look at
zkmsat least sometimes i get faster timings with my designs13:52
daveshahMoeIcenowy: Arch (AUR) provides it13:53
MoeIcenowyhaha aur provides everything ;-)13:53
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sxpertdaveshah: thanks !13:55
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daveshahThe `-nomux` isn't needed any more, other than that that example should be up to date13:55
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sxpertdaveshah: yay, my module compiles and can be placed in the fpga successfully14:18
daveshahsxpert: yay!14:25
sxpertnow, I have no idea if it works but...14:26
sxpertneed to build more things first14:26
sxpertdaveshah: for instance, need to figure out how to build staggered clocks14:27
daveshahdon't :P14:27
daveshahuse staggered clock enables instead14:27
sxpertdaveshah: have a link ?14:29
tpbTitle: Controlling Timing within an FPGA (at
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sxpertdaveshah: small nextpnr question14:53
sxpertI can only see white boxes, no traces or anything, is this normal ?14:54
daveshahThat's a defect in the ecp5 architecture, no-one has added the GUI data for the wires or switchboxes yet14:54
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sxpertdaveshah: ah, ok.14:55
sxpertwill wait ;)14:55
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MoeIcenowydaveshah: BTW any suggestions for an ECP5 board? ;-)15:09
daveshahDepends what you want to do. if you want lots of LUTs and IO15:09
tpbTitle: LFE5UM5G-85F-EVN Lattice Semiconductor Corporation | Development Boards, Kits, Programmers | DigiKey (at
daveshahULX3S is also worth a look, although a bit harder to get hold of right now15:10
daveshah if you want PCIe etc15:10
tpbTitle: LFE5UM5G-45F-VERSA-EVN Lattice Semiconductor Corporation | Development Boards, Kits, Programmers | DigiKey (at
sxpertthey just received a batch as we speak, you may be lucky15:10
MoeIcenowyoh official EVN... they're usually quite expensive...15:10
daveshahthe 85F-EVN is very good value15:10
sxpert200€ a piece. not bad15:11
sxpertwell it's a 45F, but that's the same as 85F...15:11
MoeIcenowyfor iCE40 I choose to do a UP5K board by myself (currently pending due to Chinese New Year) because all existing boards are too expensive (maybe except UPduino)15:12
MoeIcenowybut I heard that UPduino doesn't feature an onboard crystal oscillator15:12
emebIt doesn't15:13
emebgot one right here15:13
sxpertwhat's it using then ? integrated pll thingie ?15:14
emebon-chip 48MHz RC osc15:14
emebor 10kHz low freq osc if you want15:15
sxpertgood enough if you're not too timing sensitive15:15
MoeIcenowyFleaFPGA seems interesting15:15
emebI've done a few personal boards w/ LP4K/UP5K (pin compatible)15:16
emebthey're pretty easy to do15:16
emebDon't copy UPduino design tho - there are some problems with the power supply circuitry.15:16
sxpertgood to know15:17
emeband grounding isn't ideal. It works but it could be a lot better.15:17
MoeIcenowyemeb: what problem?15:17
MoeIcenowylack of decoupling capacitor on VCCPLL?15:18
emebMoeIcenowy: That's a big one.15:18
MoeIcenowyemeb: I found it's fixed in 2.015:18
MoeIcenowyI currently put a 104 and a 106 for VCCPLL on my board15:18
emebYep. Plus diode/cap reversed on Vpp ckt15:19
emebdidn't put cap on FPGA side of diode.15:19
MoeIcenowyemeb: Y?15:19
emebwhy what? I don't know why upduino did it that way, but it doesn't provide good bypass due to high impedance of diode on half wave of ripple.15:21
MoeIcenowyI think the cap should be the FPGA side, not the VCC3V3 side...15:22
MoeIcenowyfrom my (limited) experience cap should be near the chip...15:22
emebbut on upduino it's not.15:22
MoeIcenowyoh sorry15:22
MoeIcenowyI misread your sentence15:22
MoeIcenowyyou mean "UPduino didn't put cap on FPGA side"15:23
MoeIcenowyI read it as "Don't put cap on FPGA side"15:23
MoeIcenowychecked... not fixed on UPduino 2.015:23
emebSorry for confusion.15:23
MoeIcenowyemeb: no sorry15:23
MoeIcenowyjust my mother tongue is not en15:23
emebI'm sure it's better than my understanding of your language. :)15:24
* emeb speaks toddler-grade german plus some spanish. :P15:24
MoeIcenowyat least they're all Indo-European15:24
emebI suspect I'd be useless with anything that didn't use roman alphabet.15:25
MoeIcenowyBTW what's VPP_2V5 for?15:27
MoeIcenowyprogramming the NVCM?15:27
emebThat would be my guess.15:27
daveshahIt's also needed for a few other bits and pieces15:27
MoeIcenowy(to be honest I do not like any kind of OTP15:28
daveshahIn particular trimming for the oscillators is read from NVCM at boot15:28
MoeIcenowy(I do not like irreversible things15:28
MoeIcenowydaveshah: oh15:28
daveshahIf Vpp_2V5 is bad then the oscillator frequency will be way off15:28
emebGood for saving pennies on high volume stuffs15:28
emebbut it would be nice if it could erase15:29
emebdaveshah: didn't you figure out that osc can be tuned via the FPGA fabric?15:30
daveshahYes, it can be15:30
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emebwould be interesting to make FLL with that.15:31
emebuse 1PPS from GPS or something.15:31
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ZipCPUemeb: Been there, done that, it's not all that hard.  Requires a bit of a tracking loop.  I used a filter together with a 2nd order loop to track both phase and frequency.  It works fairly well.16:15
ZipCPUThe code to do it is part of my open arty project, at
tpbTitle: GitHub - ZipCPU/openarty: An Open Source configuration of the Arty platform (at
emebZipCPU: Yes - I've looked at your GPS-disciplined clock project before. IIRC though it's using a fixed external clock and locking a divided down version of that by putting a control loop on the divider ratio. I'm talking about locking the on-chip RC oscillator of the UP5k by controlling the tuning word which is kind of a hidden parameter that Lattice doesn't give you easy access to.16:20
ZipCPUYeah, okay, that's different.  That actually takes updated hardware to do.16:21
ZipCPUOn the other hand, you can use the GPS schooled logic to create a GPS-disciplined oscillator ...16:22
ZipCPU(It'll jump a bit every second, as currently built....)16:22
emebIt's just a wild idea. I don't know how easy it would be to control that tuning parameter in realtime - just something that jumped into my brain when daveshah: mentioned the tuning param was available.16:22
emebOn the other hand - if it is available then it could be used to lock a USB device to the SOH pulse.16:23
ZipCPUOoohh ... I definitely need to read more of the backlog ... logically controlling a tuning parameter based upon GPS input?  That would be quite vascinating16:23
emebThat's how the STM32F042 chip manages to get stable USB operation without an external crystal.16:23
emebThat would make it super cheap to put USB onto a UP5K part.16:25
emebSee here section 7 on the CRS here ->
* ZipCPU browses around16:29
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MoeIcenowyemeb: emmm on UP5K osc can sync to external signal?16:52
emebMoeIcenowy: it's not a normal feature of the oscillator, but daveshah found that there are hidden hooks on the IP core that could be used for that.17:08
MoeIcenowyhidden ;-)17:09
MoeIcenowyonly utilizable with IceStorm? ;-)17:10
emebMoeIcenowy: Probably.17:12
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emebTrying to build nextpnr on Fedora 28 using instructions at and cmake -DARCH=ice40 is failing due to not finding Boost::Python18:31
tpbTitle: Project IceStorm (at
emebAny clues on what to do next?18:31
emebI did install all the listed prereqs as defined in the instructions.18:32
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emebI also installed boost-python3 and boost-python3-devel but cmake is still unhappy18:34
emeboh wait - looks like it's just kicking out warnings now.18:35
emebOK - all happy. Nevermind. :P18:39
emeb(might want to add the boost-python3 and boost-python3-devel dependencies to the list on the icestorm page though)18:39
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emebSo, trying out nextpnr on my up5k SDR front-end. It seems to chew through it OK, but the critical ADC input path isn't meeting timing.20:28
emebI see that nextpnr doesn't use a .sdc file to specify clock freq goals but instead has a single freq argument on the cmd line. Is this the only knob available to turn?20:29
tpbTitle: nextpnr/ at master · YosysHQ/nextpnr · GitHub (at
emebdaveshah: oh cool - thanks!20:37
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emebclock constraints successfully added. unfortunately that didn't improve the final results very much. This is a pretty challenging design though - lots of giant adder trees for a CIC decimator that need to run at 50MHz.21:09
ZipCPUWhy do you need an adder tree for a CIC decimator?21:11
ZipCPUYou should be able to build that with just 3 adds as I recall21:11
ZipCPU... for any decimation21:11
daveshahYou can try adding -relut to Yosys' synth_ice40 command21:12
daveshahThis can improve QoR for some carry chain structures21:12
ZipCPUSure, you could, but if you are fighting with the hardware on this one then you are designing the CIC wrong21:13
ZipCPUCIC's should be simple to implement21:13
ZipCPU(Overflow helps)21:13
tmeissnerHi everone21:13
tmeissnerI'm at FOSDEM this eekend21:13
ZipCPUAfternoon, tmeissner!21:13
tmeissnerAnyone also there from this group?21:14
daveshahHey tmeissner, I'll be there too!21:14
tmeissnerYeah, I saw that you have a talk in the EDA room :)21:14
ZipCPUemeb: Are you at a University at all?  Check out frederic harris' book on "multirate signal processing"21:15
tmeissnerI think I'm in this room to hear some of the talks21:15
emebZipCPU: I'm not at a uni but I've got a copy of that book21:16
emebZipCPU: perhaps "tree" was the wrong term - adder chains.21:16
ZipCPUNo, that's the right term for the wrong implementation21:16
ZipCPUYou want to use two implementations similar to this one:
tpbTitle: Implementing the Moving Average (Boxcar) filter (at
ZipCPUYou shouldn't need any adder trees or adder chains at all--CICs are *REALLY* easy to implement21:17
ZipCPUIf you check out the boxcar.html page on, check out figure 3 which shows what I'm talking about21:18
ZipCPUInstead of needing to add N values together to get the next output, you add the difference of the new value with the old value that falls off the end21:18
emebZipCPU: yes - nothing fancy about the math in my CIC.21:19
emebBut the wordlenghts are large21:19
ZipCPU??  How big?21:19
emeb14-bit inputs, 8 bits growth per stage, 4 stages, so 46 bits on the output of the integrator.21:20
emebI've tried it with truncation and without21:21
ZipCPUWhat happens with truncation?21:21
emebthrow away some lsbits between the integrator and comb stages.21:22
emebjust to reduce the complexity of the comb stages.21:22
ZipCPUWhy not cascade the CICs at different rates, to keep the bit widths down?21:23
ZipCPUOh, another question, how fast does this need to operate?21:23
emebhere's one of my designs ->
tpbTitle: iceRadio/cic_dec_3.v at master · emeb/iceRadio · GitHub (at
emebthat's an older one that only uses 10-bit inputs21:24
emebI'm running this one at 50MHz in a UP5k21:24
emebiCEcube has no trouble building it21:24
emebbut yosys + nextpnr only hits about 24MHz21:25
ZipCPUWhich nextpnr?  ... as in, how recent?21:25
daveshahDoes this PR improve anything?21:25
tpbTitle: WIP: Reworking placer1 by daveshah1 · Pull Request #171 · YosysHQ/nextpnr · GitHub (at
ZipCPUdaveshah: Is that on the main branch?21:26
emebZipCPU: nextpnr built from git this morning.21:26
daveshahNo, that PR isn't merged yet21:26
daveshahThat's why I suggested it21:26
emebdaveshah: git newb here - what do I need to do to build with that?21:26
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ZipCPUdaveshah: You've gotten good results on the metrics for that, right?  Care to share any of those metrics here?21:27
daveshahemeb: run21:27
daveshahgit checkout -b daveshah1-crit_driven_placer master git pull crit_driven_placer21:27
tpbTitle: GitHub - daveshah1/nextpnr: nextpnr portable FPGA place and route tool (at
daveshahSorry, should be a newline between master and git21:28
daveshahgit checkout -b daveshah1-crit_driven_placer master21:28
daveshahgit pull crit_driven_placer21:28
tpbTitle: GitHub - daveshah1/nextpnr: nextpnr portable FPGA place and route tool (at
daveshahThen rebuild21:28
emebon it21:28
daveshahI've seen this give results within 5-10% of the Lattice tools21:28
daveshahBut large adder chains might be a bit of a weak spot atm21:29
ZipCPUemeb: Having looked at your code, I take back my initial conclusion(s) ;)21:30
emebZipCPU: :)21:30
ZipCPUYou should be able to drop bits before integration tho ... there's no reason why you need to go into there with 10 bits if you don't want 46 bits out21:30
emebZipCPU: well, in my experience it's good to start with the best dynamic range you can get, and I've got a 14-bit ADC.21:31
ZipCPUYeah ... I can understand that perspective completely21:32
emebI've got a version of this DDC running on a Spartan 6 with 100MHz 14-bit ADC inputs and a hardware AGC on the output of the CIC that gives me a nice bit of dynamic range.21:33
emebbut in the UP5k version I just carry 16-bits output and do the AGC in software21:33
emebdaveshah: OK - checked out your branch, rebuilt and reran on my design. Didn't make much difference on the timing.21:39
emebI'd be happy to bundle this up as a testcase if you'd like.21:42
daveshahThat would be great21:43
daveshahI think this is probably more of a synthesis than nextpnr issue21:43
emebCould well be21:44
daveshahAt the moment carry chains prevent a number of logic optimisations from working properly21:44
daveshahWe are investigating alternative ways of interfacing with abc to improve this21:44
emebsounds hairy21:50
emebdaveshah: testcase built - where should I send it?21:52
daveshah[email protected]21:52
daveshahGot it, cheers!21:56
emebcool - hope it's helpful.21:57
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