Friday, 2019-01-25

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shaprstill didn't get zoom installed00:06
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shaprhi ZipCPU!00:11
shaprso I'm trying to get working on the BeagleWire00:12
tpbTitle: GitHub - shapr/FPGA-Synthesizer (at
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ZipCPUDownloading it now00:12
ZipCPUgit pull didn't turn up any updates since the last ttime, some long time ago00:12
shaprfrom what you've taught me previously, I thought I could change the numbers used to do .. it's not clock division, wasn't there a different/better name?00:13
ZipCPUHmm .... don't see any Verilator C++ files anywhere around here either ...00:13
shaprI found this on github, asked the author to add a license so I could use it00:13
shaprthing is, I have the same digilent pmod the author used00:13
ZipCPUsynthesizer.v is the top module?00:13
shaprbut a different clock speed00:13
ZipCPUOoohh, okay00:14
shaprI think so?00:14
ZipCPUDo you have all the specification sheets?00:14
shapryes, I can get the link00:14
shaprit uses i2s00:14
shaprthis one:
tpbTitle: Pmod I2S2: Stereo Audio Input and Output - Digilent (at
shaprthis claims to be the manual:
tpbTitle: Pmod I2S2 Reference Manual [Reference.Digilentinc] (at
ZipCPUYeah ... that's only part of what you need as I recall00:15
shaprin our previous discussion, daveshah pointed out that the line that says "500MHz" is wrong00:15
shaprthis line:
tpbTitle: FPGA-Synthesizer/synthesizer.v at master · shapr/FPGA-Synthesizer · GitHub (at
ZipCPUI only see 50MHz on the reference page, so that would make sense00:16
shaprI think that becomes important when i2s is involved:
ZipCPUKeep going00:16
tpbTitle: FPGA-Synthesizer/pmod_out.v at master · shapr/FPGA-Synthesizer · GitHub (at
ZipCPUHmm ... okay ...00:17
shaprI vaguely recall that this was developed on a Xilinx board, but I have forgotten the details of our previous discussion00:17
ZipCPUDo you have a trace of that code at all?  (pmod_out that is)00:18
shaprI do remember we stopped when you pointed out that the *phase* of a signal must be preserved, I can't just change the divider numbers however I like00:18
shaprI have nothing00:18
shaprexcept this source, and a burning desire to get it working on the beaglewire00:18
shaprI also have nearly zero clue about FPGA design, just what I've heard here, and read in your tutorials.00:18
ZipCPUOk, if you've read the tutorials, do you remember how cover() works?00:19
shaprI do not00:19
* shapr quickly opens the tutorials00:19
ZipCPUI start discussing cover() in lesson 300:20
ZipCPUEver after that, we use it as part of our verification steps00:20
shaprI pretty much skipped the verification parts... figured I wasn't up to that yet00:20
ZipCPULet's start that here: Add a line `ifdef FORMAL, followed by an `endif // FORMAL, and then we'll add some more between those00:20
ZipCPUSpecifically, let's create a 10 bit counter: reg [9:0] counter; initial counter = 0;00:21
shaprin pmod_out.v?00:21
ZipCPUalways @(posedge i_clk) counter <= counter + 1;00:21
ZipCPUYes, in pmod_out.v00:21
ZipCPUThen you can say, always @(*) cover(counter == 10'd350); // for example00:21
ZipCPU(You do have SymbiYosys installed, right?)00:22
shaprshould I add the always code later in the file like the rest of the code?00:22
shaprer, I don't think I have SymbiYosys installed00:22
shaprbut I can install it.00:22
ZipCPUYou'll need it installed to do this00:22
ZipCPUInstalling it requires the installation of some other things as well ... might take a while00:22
ZipCPUI can do this here if you'd rather, and then just post the results ....00:23
shaprok, seems to be installed00:23
shaprlast night I built and install icestorm, yosys, arachne-pnr, and nextpnr00:23
shaprshould have asked for a list of requirements00:24
shaproh, more pieces need installing00:24
ZipCPUSymbiYosys also requires yices and boolector, with options for z3, avy, suprove, and some others00:25
ZipCPUWe'll work with what you have00:25
shaprwell, six core Xeon00:25
shaprso glad clifford's software all supports make -j N00:26
ZipCPUOk, let's see if I can get a trace now ...00:26
ZipCPUIt's running ...00:26
shaprwhat are you getting a trace for?00:27
shaprI think I'm missing lots of context00:27
ZipCPUI just want to see what this thing does00:27
shaproh ok00:27
ZipCPUIt helps to be able to visualize things00:27
shaprthe way I understand synthesizers, you have several types of waveforms, square/sawtooth/?00:27
shaprand you stick them together to make noise00:28
shaprand the rest of this code talks to the pmod via i2s00:28
ZipCPUOk, I have a screen shot to share ...00:29
shaprooh yes?00:29
tpbTitle: Imgur: The magic of the Internet (at
shaprmy room is heating up while I build z300:30
ZipCPUThat shows you the code modifications to pmod_out.v, and the sby file I created00:30
ZipCPUI named the sby file: pmod_out.sby00:30
ZipCPUTo run, just type: sby -f pmod_out.sby00:30
* shapr takes notes00:31
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ZipCPUThen to view the trace, type: gtkwave pmod_out/engine_0/trace0.vcd00:31
ZipCPULooks like our trace isn't quite long enough ;)00:31
shapryou can tell that because one of the lines only makes a single transition from zero to one?00:32
shapris that right?00:32
ZipCPUReally long traces are a challenge to formal.  While creating a trace is easy, getting a long one can take some work00:32
ZipCPUYes, that's right00:32
shaprsclk to be specific00:33
ZipCPULet's see if I can exhaust (i.e. formal) out to 2052 steps ... usually this is too far ...00:33
ZipCPUWell, not just the sclk, but also the lrclk00:33
ZipCPUThe lrclk should toggle with every switch from the left speaker to the right speaker00:33
ZipCPU(and back again)00:33
shaproh, I hadn't noticed lrclk00:33
ZipCPUI've made it to 1200 ... still going ...00:34
ZipCPU... it's starting to slow down ....00:34
shapruh oh00:35
ZipCPUI asked it to go to 2052.  Normally, the longest trace I do is about 300 steps or so00:35
ZipCPUUsually those traces really load the system--it's much easier to get a long trace via simulation than formal00:35
ZipCPUI'm up to about 1800 now ...00:36
shaprmaybe there's a bug?00:36
ZipCPU... and just realized there is a bug and this isn't going to work ... I created a 12'bit counter, and I wanted an 11'bit counter ...00:36
shaprthat is, perhaps the transition doesn't happen because of a bug in the verilog?00:36
shaprhow could a too-large counter affect this?00:37
ZipCPUNah, I'm covering a counter--not a transition00:37
ZipCPUUsing the cover statement, I'm asking the formal tool to find a way, any way, to make the statement true00:37
shaprhow do you know what size counter you need?00:37
shaproh right, SMT solver00:37
ZipCPUcover(expr); /// finds anyway to make expr true00:37
ZipCPUTo see your lrclk_count "tick", you'll need at least 1600 steps00:38
ZipCPULet's let this run again, and chat about the tutorial00:38
ZipCPUYou say you've read through the tutorial?00:38
shaprI skipped all the parts about formal anything :-/00:39
ZipCPU... and you expected your code to work?  ;)00:39
shaprI expected code to blow up in creative ways that would teach me something00:39
ZipCPUSee, that's what formal is for: to get the code to blow up in strange and creative ways--but where and while you can watch it00:40
shaprok, fair point00:40
ZipCPUWhen the code blows up in strange ways on the hardware, you might wonder what's going on and have no way to figure it out00:40
ZipCPUDoesn't Haskell have a sort of "correct-by-design" methodology within it?00:40
shaprit does, but you get to choose your level of correctness00:41
ZipCPUTell me, how so?00:41
shapryou can ignore all the safety if you want, or you can use the type system to check everything00:41
ZipCPUDo you tell it what to check, and what checks need to be valid?00:41
ZipCPU(Yes, there is a reason to my topic diversion here ...)00:42
shaprsort of, you could use a list in all sorts of ways, or you could define a datatype that acts like a list but constrains how you can use thta list00:42
ZipCPUHow about a counter?  Can you create a counter and then insist that it stay between 0 and say 62?00:42
shapryou can, yes00:42
shaprthough it's not simple to constrain a value like that, it's doable00:42
ZipCPUI ask because formal methods are something kind of similar to that00:43
ZipCPUBy constraining values to only those values something should have, and expressing relationships between things using formal, you can guarantee that when you place your design on actual hardware that it works00:43
shaprfrom what I know about SMT solvers (such as z3) you can ask it to find some combination of inputs that sets certain values to true or false00:43
shapryou're convincing me :-)00:44
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tpbTitle: Imgur: The magic of the Internet (at
ZipCPUThere's our updated trace00:44
ZipCPUYou can now see the lrclk toggle00:44
shaprit's long00:44
ZipCPUWell ... yeah00:45
ZipCPUThat was part of the hassle00:45
ZipCPUI would've expected that the LRclk needed to toggle with the rise in MCLK00:45
ZipCPUI might need to go back to the spec to verify that though00:45
* shapr looks at
ZipCPUHave you looked at this at all:
ZipCPUHeheh ... okay, let's start at the top00:46
shaprthe wikipedia page for I2S shows a timing diagram00:46
ZipCPUFirst things first with any project or hardware.  Once you get/acquire/purchase hardware, the first thing you want to do is to gather some files together.  Among these files are the schematic for the board, and the data sheets for all of the chips on the board00:47
ZipCPUAlso grab any documentation the vendor provides00:47
ZipCPUGrab this at the beginning of any project, lest the vendor make updates to things and not (necessarily) tell you about them.00:47
shaprah, like vendoring a library when building an application00:47
ZipCPUNot familiar with the term00:48
shaprget a version of a library saved locally so when you become familiar with its bugs, etc things don't change out from under you00:48
ZipCPUThat said, most of my projects have a core directory structure with two entries: refs/ for all of these reference files, and trunk/ for all of my project files (left over from those old svn days)00:48
* shapr makes more notes00:49
ZipCPUSome projects also have a third directory, xilinx/, in which I force the vendor to place all their specific stuffs into00:49
shaprwhy so?00:49
ZipCPUThis directory is not covered under git00:49
shapris that for generated outputs?00:49
ZipCPUThat makes it easy to blow it away and rebuild it, without worrying about damaging any source files00:49
ZipCPUIt's for the project file, generated outputs, reports, etc00:50
ZipCPUMost of the fun parts of a project are within the trunk/ directory00:50
shaprright, makes sense00:50
ZipCPUWithin that directory you get an rtl/ subdirectory for all the Verilog, a bench/cpp for all the C++ test bench stuffs, and a bench/formal for all my sby files and a Makefile to run them00:50
ZipCPUIf software is involved in the project (other than the bench tests), I'll often create a sw/ directory.  sw/host will hold the things that run on my host (i.e. PC) computer00:51
shaprdo you also have a top level Makefile so you can make clean to blow away generated files in xilinx/ ?00:51
ZipCPU(I had someone try and run PC programs on the ZipCPU, so I make a distinction there)00:51
ZipCPUOne of the items on my bucket list is to finally figure out how to "make" a Xilinx project00:52
ZipCPUI haven't figured it out yet, although it doesn't look all that hard to do00:52
ZipCPUThe other problem with removing the xilinx/ directory is ... some of the items within there can take many minutes to build.  You don't normally want to delete it therefore, although there will be times when Vivado isn't treating you nicely and ... you get the picture.00:53
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ZipCPUSo for this project, you really need a bench/formal directory (to make sure the surprises happen where you can watch and understand them) and a bench/cpp directory (for long term simulation)00:53
ZipCPUThe files themselves can be moved into an rtl/ subdirectory00:53
ZipCPUThis doesn't need to be done now00:54
ZipCPU(Perhaps when we are done000:54
* ZipCPU pulls up the spec sheet pdf he downloaded00:54
ZipCPUDid you download the Cirrus Logic spec sheet?00:54
shaprno, I've been building my way towards SymbiYosys00:55
* shapr downloads00:55
shaprok, got it00:55
ZipCPUCheck out page 1000:55
shaprI'm accustomed to working at the adafruit level00:55
shaprLady Ada tends to make clear documentation meant for newbies00:55
ZipCPULol ... this is the level I've been successful working at00:55
ZipCPUThis is also how I've managed to answer so many questions on Digilent's forums--by looking for the underlying spec sheets and reading them00:56
shaprwhat's a left-justified interface?00:56
* ZipCPU hasn't answered nearly as many Digilent forum posts recently00:56
ZipCPUMost significant bit first00:56
shaproh, huh00:56
shaprnever would have guessed that00:56
shaprthere are two different chip numbers00:57
ZipCPUThat's one of the big things about I2S ... by placing the MSB's to the left (i.e. first), you can send only as many bits as you have and then just stuff things with zeros00:57
shaprdoes this mean there are two chips in the pmod?00:57
ZipCPUIt means the vendor built two chips but only put the time into writing one spec00:58
ZipCPUWhy write two specs if you can stuff all the information into one?00:58
shaprso next step is to figure out which chip is in the pmod I own?00:58
ZipCPUExactly!  That should be marked on the schematic00:58
shapraha, 534300:58
shapraccording to the digilent webpage at least00:58
shaprthe chip difference appears to be something about the lrclk being to the left?00:59
shaprwhat should that tell me?00:59
ZipCPUOk, I like your I2S chip ... there's no nasty set of 50k registers to set up in order to do anything useful00:59
ZipCPUWhat page are you reading that from?01:00
* shapr opens a window to keep his laptop from overheating01:00
shaprsame page 1001:00
shaprI'm trying to see the difference between the cs5343 and the cs534401:00
ZipCPUYeah, okay, I see it01:00
shaprthat is, what's different between the top and bottom timing diagrams?01:00
ZipCPUThe difference is that on one chip, the MSB takes place while LRCLK changes, and on the other chip it takes place after LRLK changes01:01
ZipCPUWhile the change is minor, it's something you'll need to knwo01:01
shaprand the chip I have is where LRCLK changes before MSB is sent01:02
ZipCPUSo ... what can we learn from this ...   usually there's some good timing information ...01:02
ZipCPUIdeally you'd want to formally verify that's the case01:02
shapris it important to notice the *phase* of these signals as well?01:02
ZipCPU... or rather, that such is the case of what pmod_out produces01:02
ZipCPULet's look up t_sclkw and t_stp01:02
shaprif sclk were inverted, would I still be able to send audio?01:03
shaprprevious page01:03
ZipCPUNot sure01:03
ZipCPUUsually my goal is to follow the diagram given on a page like this, rather than to divert from it01:03
shaprdoes duty cycle imply the max or min window of time something has to change?01:03
ZipCPUIf you make the waveforms match this one, you know the design will work01:03
ZipCPUIs your clock, i_clk, running at 50MHz or 100MHz?01:04
shaprBeagleWire stock is 100MHz according to the docs01:05
ZipCPUPerfect!  Our trace has the right timeunits then01:05
ZipCPU(There's got to be a way to change the timeunits, but 10ns has always worked for me)01:05
shaprer, what?01:06
ZipCPUSo now we can measure how long the mclk is, as an example01:06
ZipCPU(You can see from the picture the duty cycle is 50% ..)01:06
ZipCPULooks like 500ns for MCLK01:06
shaprsomewhere in the verilog we set the unit to 10ns?01:07
shapror is this for the formal stuff?01:07
ZipCPUThe 10ns was the step size in the trace the formal stuff created01:07
ZipCPUThere's got to be a way to match it to your design ... I've just never done it01:07
shaprok, that's where they need to match01:07
ZipCPUSo, if your design was using 50MHz (20ns) ... the two wouldn't match at this point01:08
shaprhow does 50MHz translate to 20ns?01:08
shaproh, each clock is X ns?01:08
ZipCPUEach clock period is some number of nanoseconds.  So take 1 / (CLOCK RATE) and you should get 10e-9 for a clock rate of 100MHz, or 20e-9 for a clock rate of 50MHz01:09
shaprok, that makes sense01:09
ZipCPUI'd like to know how the MCLK corresponds to a particular sample rate ... but I'd need to read the data sheet more01:09
ZipCPUThat should be an important part of your design -- matching the two01:10
ZipCPUIdeally, you should be able to play a tuning note from whatever musical instrument, and also play a note on your FPGA and the two pitches should match01:10
ZipCPULet's see ... you'd be running this in slave mode, right?  (Can't see why not)01:11
shaprno clue01:11
* ZipCPU was looking at the wrong half of the chart01:11
ZipCPUOk, then let me tell you: Yes01:12
ZipCPUSince you are providing the clock to the chip, the chip will act as the slave and you the master01:12
shaprmeans the clock is coming from the beaglewire?01:12
shaprok, got it01:12
ZipCPUSo the chip offers two useful modes for this SCLK period: Single-speed 384x mode, and single-speed 256x mode01:12
ZipCPUOohh ... the SCLK period needs to directly relate to the sample rate (see the equation?)01:13
shaprhow do you know they're useful for this?01:13
* shapr looks for the equation01:13
ZipCPUIt's about 5-lines from the bottom of page 901:14
shaproh, I see it01:14
ZipCPUAn SCLK period of 500ns corresponds to a 31.25kHz sample rate if you run the equation and solve for Fs01:14
ZipCPUThe last three lines give us some nice formal properties we can work with01:15
shaprwhy is there a negative value there?01:15
ZipCPUYou can see from the trace we have SCLK falling on the LRCK edge, so that's good01:15
shaprsclk falling to lrck edge01:15
shaprwhy is that good?01:15
ZipCPUIt's just that you've got some slop there01:15
shaproh, ok01:16
ZipCPUGiven when LRCK changes, SCLK must change within 20ns of that--two clocks basically01:16
ZipCPUIn the trace we just generated, SCLK is falling at the same time LRCLK is changing--so that's perfect01:16
ZipCPUWe can quantify that as: always @(posedge i_clk) if ((f_past_valid)&&(!$fell(o_i2s_sclk))) assert($stable(o_i2s_lrclk));01:17
shaprwait, I don't see sclk changing when lrck changes in the trace01:17
shaprsclk changes at 0.5 ns, right?01:18
shaprer, microsecond, sorry01:18
ZipCPUHmm ... yeah, you are right01:18
ZipCPUI got it confused with the MCLK01:18
ZipCPUSo, that'd be broken then--good catch01:18
shaprI'm just trying to verify that I can at least see what you're saying :-)01:19
ZipCPUGood, good01:19
ZipCPULooks like I mucked around with it.  (I'd forgotten about that) Let me revert back to what's in the repo and see if it changes anything01:20
shaprhm, super_prove_build fails to build, I can figure that out later01:20
ZipCPUYeah ... I've struggled to get that one to build01:21
ZipCPUI don't use it, so it hasn't bothered me much01:21
ZipCPUI really spend all my time with yices and boolector01:21
shaprsince I don't know what pieces I'll need, I'm just building everything in clifford's list01:21
* shapr warms the room with make -j12 in extavy01:22
ZipCPUSo, ... I reverted back to the repo's version and now I'm getting a bunch of bugs ...01:23
shaprso right now you're trying to confirm that the verilog code in the repo matches the requirements in the spec sheet?01:23
shaprnot surprised...01:23
ZipCPUWell, where else would you start?01:23
ZipCPUThis is how I get things to work ... read the spec sheet, look specifically for the pretty drawings, and check the timings01:24
shaprI don't know where I'd start, so I'm confirming that I do understand what and why01:24
ZipCPUOk, found the bug ... you can't initialize sig_temp to sig because sig isn't constant.  (That's on my line 25)01:25
ZipCPUshapr: Yep!  Start with the schematic and the data sheets01:25
ZipCPUMatch the pins on your FPGA to the pins on the data sheet via the schematic01:25
ZipCPUUse the schematic to find the data sheets of relevance, then look for the pretty pictures01:25
ZipCPUUsually, there's also some kind of instructions as well as the pictures--things like, set this register to this to accomplish that01:26
shaprearlier you said this doesn't need a bunch of that?01:26
ZipCPUFor example, my ethernet chip has a register that I can use to make the port lights blink manually01:26
shapr"no nasty set of 50k registers to setup"01:26
shaprhuh, interesting01:26
ZipCPUExactly.  This chip is unusual among the I2S chips I've looked at, since it doesn't have an I2C (not I2S) requirement allowing/requiring you to (re)configure it01:27
shaprmorse code :-D01:27
ZipCPUWell ... this is why I haven't started my own I2S journey01:27
ZipCPUIt's not because I don't have the code, and its not because I don't have a board with I2S on it01:27
ZipCPUIt's because I can't decide how to go about configuring the I2S that I have01:27
ZipCPUor rather ... the sound chip (with the I2S ports) that I have01:27
* ZipCPU is still running the 2k samples to see if he destroyed the SCLK ...01:28
ZipCPUOk ... cover just passed, let's look at this new/updated trace ...01:29
ZipCPUOk, sclk is toggling with a 1us period01:30
shaprwhat does cover(&counter); actually do?01:30
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tpbTitle: Imgur: The magic of the Internet (at
ZipCPU&counter is an expression that will only ever be true if the *and* of all the bits in the counter is 1'b101:31
ZipCPUcover() is a formal operator that instructs the formal tools (when using mode cover) to exhaustively examine your design to see if there is some way to make the expression within true01:32
ZipCPUSo ... I'm using it to quickly get a trace of 2048 timesteps01:32
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ZipCPUIf you now zoom in on the LRCLK transition, you can see that it takes place at a time where SCLK falls as well01:33
* ZipCPU backs up to take a peak at the rest of the project01:34
shaprI'd be perfectly happy being able to send noise out of the pmod01:34
ZipCPUBe careful ... you might find yourself sending silence out of it, and not realizing what you've done01:35
ZipCPUDid you write the osc_sine.v function?01:35
shaprI wrote zero of this01:35
shaprlike I said, found it on github, seemed like the thing I wanted, asked the author to add a license01:35
ZipCPUI'm not sure I know of any hardware that can do a divide01:35
ZipCPUSome hardware can do multiplies, but divides?  Those are ... two steps past reality01:36
shaprohh, that line 19 in osc_sine.v ?01:36
ZipCPUNo, not that.  All the initial stuff is done by the synthesizer, not the hardware01:36
shaprso that'll need to change for it to work on this ice40?01:36
ZipCPUI'm more worried about linse 39 and 4101:36
shaprI think this was written for a Xilinx Zynq board?01:37
ZipCPUThose are divides by constants, so they might work ... since you could turn them into multiplies01:37
ZipCPUYeah, this might not work on an ice4001:38
ZipCPU(Other things would)01:38
ZipCPUFor example, what equation defines cos_curr from start to finish?01:38
* shapr thinks01:38
ZipCPUcos_curr = cos_last - (sin_last / denom);01:38
shaproh, right01:38
ZipCPUOoohh ... line 50?  That'd be *really* hard to do ... accept an arbitrary input, and divide a value by it?01:39
shaprnever crossed my mind that some verilog only works on some hardware01:39
ZipCPU(Remember: divides are hard.  Multiplies only work with special purpose hardware often called "DSP"s)01:39
shaproh, that's what DSPs do?01:39
shaprI figured they did FFTs01:39
ZipCPUMost iCE40's don't have DSP's, although I think the 5k's have them01:40
ZipCPUYes, the DSP's can be used to do FFTs--since you can't get around the multiplies within the FFTs01:40
shapr"Lattice iCE40HX4K - TQFP 144 Package"01:40
shapraccording to the beaglewire description01:40
ZipCPUIn my own FFT implementation, I have a minimum requirement of log_2(FFT_SIZE) multiplies01:40
ZipCPUTreat that as an HX8K part ;D  It's good for it01:41
shaprman, I thought software devs got picky about stuff01:41
ZipCPU(The chip is identical)01:41
shaprdoes that mean it has DSPs?01:41
ZipCPUYou don't have any DSPs at all01:41
shaprwell then01:41
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shaprno div for me01:41
ZipCPUThat doesn't mean you can't do this, it just means you'll need to switch algorithms01:41
ZipCPUFor example, why not do all the division on the BBB?01:41
shaprer, ok?01:42
ZipCPUThe BBB should be able to set the frequency of what you are doing, why not?01:42
shaprer, I guess?01:42
ZipCPUHave you seen my NCO article?01:42
shaprdon't think so01:42
* shapr reads
ZipCPUYes, that one01:42
ZipCPUIt makes the math easy01:43
shaprheh, "embedded *embedded* applications"01:43
* ZipCPU wanders off to go fix that01:43
shaprMy mother was an English teacher, I had that kind of thing drilled into me.01:43
shaprI could put up PRs to fix your blog if you like :-)01:44
* shapr spots more typos01:44
ZipCPUMy problem is ... I read things things in all kinds of formats ...01:44
ZipCPUI first build it in markdown, then add links, then try to read it on the page but often end up switching to markdown, ... etc, etc, etc01:44
shaprmakes sense01:44
shaprI often see what I think I wrote01:45
shaprso, how do I set the frequency from the BBB?01:45
ZipCPUGood question, let's go back to the schematic01:45
shaproutput a single frequency from the verilog, and have an input signal to move the frequency?01:45
shaprthat wouldn't require division?01:46
ZipCPUIt sort of depends upon how much work you want to put into the communication01:46
ZipCPUNo division01:46
shaprcould I write verilog that acts like division? or would that be too slow?01:46
shaprI assume I'll have space01:46
ZipCPUYou actually do have space.  I've placed a divide unit onto an 8k before with space left over for the CPU that uses it :D01:46
ZipCPUWhat you don't have is time01:46
shaprdivide unit takes multiple cycles?01:47
ZipCPUThe code you have asks for a division to be accomplished in one clock cycle01:47
shaprman, this is weirder than a C programmer writing Haskell01:47
ZipCPUMy divide unit takes (roughly) 32 clock cycles to divide a 32'bit number by another one01:47
shaproh wow01:47
ZipCPUAnd the multiply unit?  That's crazier01:47
ZipCPUI finally got a *REALLY* good multiply unit to work on my ice4001:47
ZipCPUIt costs half as much as any other one I might try01:48
ZipCPUHowever, it also costs about N+2 cycles for an N-bit multiply01:48
shaprmultiply can be done in a single cycle, but division only if you have a DSP01:48
ZipCPUNo, other way around01:48
shaprdivision can be done in a single cycle?01:48
ZipCPUMultiply can be done in one cycle if you have a DSP, division always takes many cycles (or a *REALLY* slow clock)01:48
shaprmy brain is getting full01:49
ZipCPUSo, since the iCE40hx8k doesn't have DSP's, my multiply algorithm takes N+2 clocks for an NxN multiply01:49
ZipCPUThis is good, right?01:49
shaprexactly what I wanted!01:49
shaprdrinking from the firehose!01:49
ZipCPUOk, I do have a recommendation for you:01:49
shapr1. read the formal parts of the zipcpu tutorials01:49
shapr2. install all the tools01:49
ZipCPUGo back through the tutorial, and do *all* the exercises.  Get them to work on your hardware01:50
shapr3. read ALL the zipcpu tutorial blog posts01:50
ZipCPUThat'll give you several examples to work with that are (roughly) similar to this one01:50
ZipCPUIt'll also give you a base to work with, so that you can understand this problem when you get to it01:50
ZipCPUDo you have a serial port to work with?01:50
shaprI sort of wish the beaglewire had DSPs, but I'm sort of glad it doesn't, I have to learn the real stuff01:50
shaprer, sort of01:51
ZipCPUSort of?01:51
shaprI have an FTDI cable01:51
shaprI have some arduinos that only take serial input, don't have their own FTDI chips01:51
shaprI may have a serial pmod01:51
shaprI bought a whole bunch01:51
ZipCPUSerial pmod is good ... I think it's calld a Pmod USBUART01:51
ZipCPUDouble check the power on it though--you don't want to be fighting with the BBB's power01:52
ZipCPU(There's a jumper that needs to be set properly)01:52
ZipCPUYou might also have a serial port directly into the BBB---check your schematic01:52
ZipCPUThat'd probably be the easiest one to work with01:52
ZipCPU(Remember: Download the schematic first ... that'll tell you what's hooked up to what)01:53
shaprI don't have a serial pmod01:53
ZipCPUThe RaspberryPi as I recall had a serial port on its extension pad ... but I might need to check that01:53
shaprthey do sell a usb to uart01:54
ZipCPU(I'm checking to see if I have a BBB schematic ...)01:54
shaprthe BBB is way more complicated than the rpi, imo01:55
shapralso far more oshw01:55
ZipCPUYes, I think you are right on that account01:55
shapr(see my earlier comments in #openfpga about the closed-ness of the rpi)01:55
ZipCPUThere it is ... yes, you have a couple of UART's on your expansion header01:56
shaproh good01:56
ZipCPUThat's on the last page of the BBB schematic I have (page 11)01:56
ZipCPULooks like you might even have 4 separate UARTs ... neat.  Not sure what you'd use 4 UART's for .... but you have them01:56
shaprthen I could talk to one of my arduinos that only have serial?01:56
ZipCPUIt's also an easy way to talk to your FPGA and figure out what's going on within it, and to tell the FPGA what you want it to do01:57
shaprhow do you do that?01:57
ZipCPUThe tutorial focuses in many ways on the serial port, so having one will make your task easier01:57
shaprserial from your desktop to your FPGA?01:57
ZipCPUNot only that, but imagine running a C++ program on your desktop with calls to readio(ADDR) and writeio(ADDR, VALUE); which you can use to read and write values within your FPGA01:58
shaprsince I have the beaglewire daughterboard (cape?) perhaps some of the ice40 pins connect to uart pins on the bbb?01:58
shaprthat would be handy01:58
ZipCPUYou know, one value might set the frequency of your tone, and another the amplitude?01:58
shaprreminds me of ws2812 code I've written01:58
shapryeah, I did that for neopixels, where I'd send RGB values for each pixel01:58
ZipCPUSee ... this is another reason why you want to start with the schematic--it lets you know what toys you have to play with01:59
shaprgot slow with 144 though01:59
ZipCPUWhat did you write the code with?01:59
ZipCPUAs in, what hardware did you use to control your ws2812?01:59
shaprI was using the arduino IDE, it's sort of C++01:59
shaprI sent it text commands over the usb<->serial, and it set the ws2812 values01:59
ZipCPUOk, even better, now imagine connecting that to an FPGA.  You could toggle those lines as fast as they could go, instead of as slow as the arduino would go01:59
shaprthat would be *cool*02:00
shaprI have an unreasonable number of ws281202:00
ZipCPUIndeed, using the FPGA, you could probably toggle the lines *too fast*, so you'd need to make sure you ran at the right speed02:00
ZipCPUOoohh, even better, why not use your FPGA to toggle several of them at once? ;)02:00
ZipCPULots of possibilities there.02:00
shaprpower problems02:00
ZipCPULet's get back and focus, though ...02:00
ZipCPUStart with the serial port.02:00
ZipCPUOn the BBB, you'll use a program called "minicom" to communicate with the serial port02:01
shaprI think I have several hundred watts worth of ws2812b in various form factors02:01
shapryup, familiar with minicom02:01
shaprused that for talking to the arduinos02:01
ZipCPUDo you have any buttons on your BeagleWire?02:01
shapryes, three02:01
ZipCPUOoohhhh!!! You've got to try the button pressing project02:02
tpbTitle: File:Bw title.jpg - (at
ZipCPUSee if you can get the button counter to count backwards like I did :)02:02
shapris this a project on your blog?02:02
ZipCPUIt's one of the projects within the tutorial, leading to a discussion of timing and why it's important02:02
shaprok, any more assignments or suggestions for next time?02:03
* ZipCPU tugs at his beard02:03
ZipCPUWell, each of the tutorial lessons has an assignment or two within it02:03
shaprok, do those02:04
* shapr makes more notes02:04
ZipCPUIn all likelihood, you'll come back before you've finished with those02:04
ZipCPUDo you have any LED's on your board?02:04
shapryes, four02:04
ZipCPUPmod LED?02:04
ZipCPUFour is fine02:04
shaprhad lots of fun getting this to work:
tpbTitle: BeagleWire/top.v at master · pmezydlo/BeagleWire · GitHub (at
ZipCPUMy example I think is for 8, but the homework lesson is to adjust it down to the number available on your board02:05
shaprand this was even more fun:
tpbTitle: First verilog code that does something - Album on Imgur (at
shaprand then I figured out how to get both displays on the 2x seven segment to count up02:05
ZipCPUI've got a fun video I'm hoping to post soon--tonight perhaps even02:05
ZipCPUI managed to get my FPGA to create a scrolling FFT raster02:06
ZipCPU... and I want to share that video02:06
shaprnot sure what that is02:06
ZipCPUI took it from the middle of Beethoven's 9th, starting when the Base singer joins the orchestra02:06
ZipCPUNo?  We discussed this some time before02:07
ZipCPUIt shows frequency usage over time02:07
shaprheh, first google hit is
tpbTitle: GitHub - ZipCPU/fftdemo: A demonstration showing how several components can be compsed to build a simulated spectrogram (at
ZipCPUThe current sound is always on the right, as the display scrolls left02:07
ZipCPUYeah, that's the project02:07
shaproh, the waterfall display02:07
ZipCPUSince then, though, I've added HDMI + DDR3 SDRAM support02:07
tpbTitle: Frequency Resolution (Teaser) (at
shapryeah, my kiwiSDR has that, looks really cool02:08
ZipCPUIt's even more fun to play with02:08
shaprok, so I have a bunch of notes, and I have logs so I can go back and re-read what you've taught me02:08
ZipCPUAlthough .... evey time my security officer gets vocal with me, she seems to overload the system02:08
shaprsecurity officer? I thought you were self-employed?02:09
shaproh, I get it!02:09
ZipCPUShe's a subcontractor for Shepherd Security Services02:09
shaproh, neat02:09
ZipCPUIt's a German firm02:09
ZipCPUGet it?02:09
* shapr snickers02:09
ZipCPUJust making sure! ;)02:10
shaprso my first task is to get all the tools installed02:10
shaprand report bugs or whatever for things that don't work02:10
ZipCPUYour next task is an echo project on your serial port02:10
shaprthen do all the tutorials and homework02:10
shaprok, sounds good02:10
ZipCPUYou should be able to type into your serial port and get exactly what you typed back out --- for very little work02:10
ZipCPUThat's lesson 1 of the tutorial02:10
shaprI don't think I have any desktop/laptop with a serial port02:11
ZipCPULesson 2 works with an LED, causing it to blink once / second02:11
shaprI'll have to check02:11
shaprsounds easy enough02:11
ZipCPUUse the BBB's serial port02:11
ZipCPULog into the BBB and then start minicom02:11
ZipCPULet's see ... lesson 3 has you building your first state machine, to rotate through your LEDs--back and forth02:11
shaprdoes that mean the serial implementation gets written in verilog02:11
shaprand runs on the ice40?02:12
ZipCPUThe easy implementation in lesson 1, and then a more difficult implementation in lesson 902:12
shaprok, I'm sure I'll have more questions02:12
ZipCPUThe easy implementation just connects the transmit and receive wires together02:12
ZipCPUThat's the "easy" part02:12
shaprthat is easy02:12
shaprloopback serial02:12
ZipCPUThe harder one in lesson 9 has you decoding the serial port and then re-encoding it to send the results back02:13
shaprok, I have it all written down02:13
ZipCPUYou sure?02:13
ZipCPUHeheh ... I'll be here if you get stuck02:13
shaprok, time to build and install stuff...02:14
ZipCPUI look forward to hearing good things back from you ;D02:14
ZipCPULet me go back to playing with my raster ...02:15
ZipCPULook for a tweet with a video, if all goes well02:15
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keesjhow long does it take to like verilog (comming from VHDL) ?06:23
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ZipCPUAsk daveshah.  He's one of the few that have made the transition successfully13:48
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keesjI am looking at some examples in the icestom git repo I am looking at
tpbTitle: icestorm/checker.v at master · cliffordwolf/icestorm · GitHub (at
keesjI see next_xorshift32_state reused different times in the always block and kinda find that .. strange (compared to my understanding). I expect the next_xorshift32_state on the right side to .. only change value past the always block e.g. while the first line (28) modifies the next_xorshift32_state I expect this modification to not be visible on the next line (29)19:12
daveshahkeesj: the modification is visible because a blocking assignment (=) is used rather than a non-blocking assignment (<=)19:12
keesjam I correct and if so.. I am corret in thinking only the last line (29) actually result in something?19:12
keesjA.. ok19:13
daveshahthink of it like := with a variable in VHDL19:14
keesjand would this change be visible externally ? e.g. the stant changes be visible19:14
daveshaheh, it's complicated19:14
daveshahnot in hardware19:14
keesjok.. I (might ) get it..19:15
daveshahin simulation you get all kinds of ugly race condition possibilities that I can't exactly remember19:15
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mmsEvening fellas21:41
daveshahHeya mms21:42
mmsHas anyone done or know any comparison done between yosys and vtr?21:42
daveshahI'm not aware of any detailed comparisons21:44
daveshahLast time I looked Yosys' Verilog support was much broader than ODIN II's21:44
mmsI see21:45
mmsI guess I have to check their Verilog support, thanks daveshah21:47
daveshahIs there anything in particular you are interested in?21:48
mmsdaveshah, No. I'm really new to logic synthesis and I was looking to get an general overview of these two.21:51
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sorearmms: talks briefly about odin versus yosys22:59
tpbTitle: Qflow (at
sorearnote that standard cell technology mapping and LUT mapping are related but not quite the same problem23:00
mmssorear, thanks23:03
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