Friday, 2019-01-11

*** tpb has joined #yosys00:00
*** gruetzkopf has joined #yosys00:40
*** Vincenttl has quit IRC00:56
*** ZipCPU has quit IRC02:49
*** ZipCPU has joined #yosys02:49
*** promach has joined #yosys02:52
promachFor , why am I having error : ERROR: Invalid array access. ?  I am using yosys-smtbmc by the way02:55
tpbTitle: Ubuntu Pastebin (at
*** wavedrom has quit IRC03:07
promachI have solved this03:17
ZipCPUpromach: Uses SymbiYosys instead--it's easier to work with and offers you more verification capability03:23
promachyeah I am using sby03:24
promachZipCPU: I am now having problem resetting 2D array in systemverilog03:24
ZipCPUResetting an array .. is that even legal on any hardware?03:25
tpbTitle: Ubuntu Pastebin (at
promachI seem to have solved the resetting problem03:25
promachanother error cam eup03:25
promachcame up03:25
promachthis is a afifo03:26
promachZipCPU: I want to see how Jeff Bush implementation fares in formal verification03:27
tpbTitle: Ubuntu Pastebin (at
promachhis logic is simple but I am not sure it is working well enough03:27
* ZipCPU is struggling with internet problems right now and can't click on any links03:28
promachZipCPU: ok, 404 ?03:28
promachI will figured this out slowly then, this code is not urgent at all03:28
ZipCPUNo, my router isn't allowing my laptop to connect to the internet without going through my desktop03:29
ZipCPUIt's ... complicated03:29
promachstrange wifi router, haha03:29
*** citypw has joined #yosys03:29
ZipCPUIt's not that strange ... it worked just fine this morning03:30
*** pie_ has quit IRC03:50
promachZipCPU: successfully solved my sby setup issue04:03
promachnow I am going to focus on writing assert() and assume() , and cover() for the code04:03
ZipCPULooks like I've also succcesfully solved my router issue as well04:04
*** wavedrom has joined #yosys04:05
ZipCPUpromach: You realize that only ASIC hardware will support that FIFO clearing function, right?04:07
ZipCPUFPGA Block RAMs can't do that04:07
promachI mean with reset, you could04:07
*** citypw has quit IRC04:17
*** citypw has joined #yosys04:22
sorearasic memories can't do that either, you've just created a big array of flip-flops04:43
promachlogic [WIDTH - 1:0] fifo_data[0:NUM_ENTRIES - 1];04:45
promachsorear : what would be your recommendation ?04:45
tpbTitle: An asynchronous FIFO implementation from the book "The Art of Hardware Architecture Design Methods and Techniques for Digital Circuits" · GitHub (at
soreardunno, ->sleep04:48
promachgood, sleep is the best recommendation, haha04:49
*** rohitksingh_work has joined #yosys05:07
*** _whitelogger has quit IRC06:18
*** _whitelogger has joined #yosys06:21
*** promach has quit IRC07:10
*** rohitksingh_work has quit IRC07:48
*** rohitksingh_work has joined #yosys08:18
*** wavedrom has quit IRC08:19
*** promach has joined #yosys08:24
promachFor , why "mode cover" does not generate a vcd waveform for me ?08:24
tpbTitle: Ubuntu Pastebin (at
promachuse this paste instead
tpbTitle: Ubuntu Pastebin (at
promachsee line 39908:27
promachline 130 and 161 as well08:28
*** rohitksingh has joined #yosys08:38
*** lineprinter_ has joined #yosys08:45
*** Cerpin_ has joined #yosys08:47
Cerpin_since i know a lot of the people who work on the open ice40 tools are here: is there a way to infer something like an open-drain pin on a microcontroller with the ice40 i/o tiles?08:49
Cerpin_Err, with an internal pull-up, additionally08:49
Cerpin_I think that's the main thing I don't know how to ensure gets used, actually...08:49
Cerpin_(if there is a better channel for this, I apologize and can move my question over there)08:50
*** Kamilion has quit IRC09:12
*** Kamilion has joined #yosys09:13
*** rohitksingh has quit IRC09:29
*** rohitksingh has joined #yosys09:31
daveshahCerpin_: you should be able to do `assign q = x ? 1'bz : 1'b0;`09:32
daveshahpullup can be enabled with `-pullup yes` in your pcf file09:32
daveshahAfter set_io09:33
daveshahThis is a weak pullup, on up5k you can enable a strong pullup with `-pullup_resistor 3P3K|6P8K|10K`09:34
daveshahas desired09:34
*** vup2 has joined #yosys09:41
*** gruetzkopf has joined #yosys09:55
promachI have my previous problem using
tpbTitle: An asynchronous FIFO implementation from the book "The Art of Hardware Architecture Design Methods and Techniques for Digital Circuits" · GitHub (at
*** citypw has quit IRC10:22
*** gruetzkopf is now known as gruetze10:30
*** gruetze is now known as gruetzkopf10:30
*** tmeissner has joined #yosys10:53
*** emka has quit IRC10:58
*** leviathanch has joined #yosys11:39
*** dys has quit IRC12:00
*** rohitksingh has quit IRC12:20
*** rohitksingh_work has quit IRC12:59
tmeissnerHi everyone13:01
tmeissnerDoes anyone has experience with the bind command to bind a SV(A) module to a VHDL entity?13:02
tmeissnerThe simple case works for me, but what should I do if I have a block defined inside the VHDL entity?13:02
tmeissnerI cannot access the signals inside this block becuase it's another scope inside the architecture :/13:03
ZipCPUMorning, tmeissner!13:19
ZipCPUYes, I have experience with the bind command13:19
ZipCPUYou have a couple of options there.  You can apply another bind to the sub-entity13:19
ZipCPUYou can also use the dot notation to set values in the top entity to match particular values in the subentity.  These might only be used by the bind component.13:20
ZipCPUThat then gives you access to values within the subentity13:20
promachbind command is supported now in yosys-smtbmc ??13:25
tmeissnerIt's not a sub-entity. it's a block inside a VHDL block statement13:25
tmeissnerI'm going to have a espresso first, will look after the options after ;)13:25
tmeissnerBut tahnks anyway :)13:26
*** kernlbob has quit IRC13:26
ZipCPUpromach: Try SymbiYosys--it's much easier to use than yosys-smtbmc13:27
ZipCPUSymbiYosys can be used to drive yosys-smtbmc, but not all engines use yosys-smtbmc.  SymbiYosys will select and drive the correct engine for you13:28
promachSymbiYosys supported bind command now ?13:29
ZipCPUThe commercial version has for quite some time now13:32
promachnot all people have the commercial one though :|13:33
ZipCPUThe commercial version has full SV and VHDL support, to include concurrent assertions13:34
promachso the non-commercial, free version which is non-verific does not support  bind  , [*1:$]  , |=>  , |->  , etc..   ?13:35
*** celadon has joined #yosys13:42
*** rohitksingh has joined #yosys13:47
*** m4ssi has joined #yosys14:28
*** pie_ has joined #yosys14:28
*** m4ssi has quit IRC14:38
*** citypw has joined #yosys14:39
*** m4ssi has joined #yosys14:40
*** kbeckmann has joined #yosys14:59
*** m4ssi has quit IRC15:03
*** m4ssi has joined #yosys15:04
*** tmeissner has quit IRC16:03
*** rohitksingh has quit IRC16:08
*** pie_ has quit IRC16:27
*** leviathanch has quit IRC16:43
*** wavedrom has joined #yosys17:07
*** m4ssi has quit IRC17:15
*** dys has joined #yosys17:17
*** rohitksingh has joined #yosys17:54
*** rohitksingh has quit IRC19:07
*** citypw has quit IRC19:13
*** wavedrom has quit IRC19:13
*** sigwinch has joined #yosys19:25
*** sigwinch_ has quit IRC19:28
*** d0nker5 has joined #yosys20:01
*** X-Scale has quit IRC20:27
*** X-Scale` has joined #yosys20:29
*** develonepi3 has quit IRC21:54
*** pie_ has joined #yosys22:03
*** pie_ has joined #yosys22:04
*** pie_ has quit IRC22:12
*** voxadam has quit IRC22:12
*** voxadam has joined #yosys22:14
*** develonepi3 has joined #yosys22:20
*** voxadam has quit IRC22:50
*** powerbit has joined #yosys22:53
*** TFKyle has quit IRC23:34
*** TFKyle has joined #yosys23:39
*** d0nker5 has quit IRC23:52

Generated by 2.13.1 by Marius Gedminas - find it at!