Monday, 2019-01-07

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sigwinch_Good morning, #yosys!08:45
daveshahMorning sigwinch_!08:45
sigwinch_I was asking myself how to properly have a counter have the correct width, based on the number of cycles I want to count, and especially to get rid of a warning when I compare against "number of cycles minus one". Here's what I came up with, and I wanted to ask if that's the proper way or hopelessly ugly:08:47
tpbTitle: [VeriLog] verilog integer width - (at
daveshahSo personally I'd never worry about such a warning08:49
daveshahI think an alternative way might be to do (NCYCLES-1)[CYCLE_CTR_BITS-1:0]08:50
sigwinch_Ah, good idea, never thought of that (bit-indexing a integer literal).08:51
swetlandI believe you need $clog2(N+1) if N could be an exact power of two09:03
swetlanddaveshah: I like the warning in general as it catches assignments of mismatch net-sizes to each other, but it does get entertaining when params/constants are involved09:04
swetlandas I am reminded elsewhere, don't need the +1 on the clog2 if N-1 is the max value in use09:14
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sigwinch_daveshah: verilator doesn't like (123)[NBITS-1:0] ...10:29
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sigwinch_...and yosys doesn't like typedefs ;-).10:31
swetlandtry this in verilator:10:32
swetlandlocalparam NCYCLES_1 = NCYCLES - 1;10:32
swetlandit seems to be willing to slice a param but not an arbitrary expression10:33
sigwinch_:-) Very good. Seems to make both yosys, iverilog and verilator happy! Thanks!10:36
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swetlandthis has been the adventure of verilog/systemverilog for me -- finding the union of features/syntax/dialect that all the tools I want/need to use can understand10:37
tpbTitle: [VeriLog] verilog counter with dynamic width, 0..(N-1), no warn - (at
swetlandso there's a neat trick for this that someone pointed out to me recently -- if you load the counter to max and then detect the underflow (making the counter one bit wider than you need to be), you don't need an n-bit-wide comparator to detect the trigger/reload -- you just trigger on underflow10:45
tntsigwinch_: in general if you don't need the value, make counter 1 bit wider, init to xxx-2, doing a decrement and look for the msb going high. Avoids the need for a comparator.10:45
tntArf ... was too slow to type :10:46
sigwinch_That's a very useful remark, thanks tnt!10:46
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sigwinch_(and of course swetland ;-) ...)10:52
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swetlandtnt's explanation was much more succinct -- worth the wait ^^10:55
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sigwinch_ - I would have written a shorter letter, but I did not have the time.11:02
tpbTitle: Blaise Pascal - Wikiquote (at
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shaprZipCPU: hey! newbie verilog question ... is #mystorm a better place for me to ask?19:01
ZipCPUNo, this is fine ... what's up?19:01
shaprrestarted my FPGA class for the year19:02
FL4SHKFPGA class?19:02
shaprI want to get this FPGA-Synthesizer working on my beaglewire19:02
FL4SHKIn school?19:02
shaprFL4SHK: yeah, I teach a Monday FPGA class here at my job19:03
shaprer, no19:03
FL4SHKoooh teach19:03
shaprFL4SHK: I don't actually know anything about FPGAs!19:03
ZipCPUFL4SHK: Corporate lunch time, sweet, huh?19:03
shaprthat makes it more challenging :-P19:03
FL4SHKwhen I was doing my MS degree I did a bunch of HDL dev19:03
ZipCPUOk, keep going ... synthesizer19:03
shaprFL4SHK: I did convince several of my coworkers to buy their own BeagleBone + BeagleWire19:03
ZipCPUI have the BBB ... just not the beagle wire19:04
shaprZipCPU: I will happily send you one and some cash19:04
shapryou just have to remind me of your contracting fees again19:04
shaprI forked an existing FPGA-Synthesizer19:04
shaprbut the whole codebase relies on ... I think a 2MHz system-wide PLL19:05
shaprand the BeagleWire has a 1MHz? maybe it's 200MHz and 100MHz19:05
shaprin any case, all the clock division is done explicitly from the PLL on a Xilinx board19:05
ZipCPULet's see ... you should be able to run the BeagleWire at about 50MHz, maybe more19:05
shaprZipCPU: so my question is, do I need to just divide the existing counts by the difference between the Xilinx and BW clock speeds?19:06
FL4SHKIs the BeagleWire an FPGA board?19:06
shaprFL4SHK: yes!19:06
FL4SHKI see19:06
FL4SHKI'd never heard of it19:06
tpbTitle: BeagleWire | Crowd Supply (at
shaprFL4SHK: I chose it because you can install yosys directly on the board19:06
shaprand my earlier Haskell classes ran into problems installing on a wide variety of operating systems19:06
ZipCPUThis is good ... keep going19:07
shaprZipCPU: so I think this says the board this was built for is 500MHz:
tpbTitle: FPGA-Synthesizer/synthesizer.v at master · shapr/FPGA-Synthesizer · GitHub (at
shaprand I think this says the BeagleWire is 100MHz:
tpbTitle: BeagleBoard/BeagleWire - (at
ZipCPUYou'll never get the iCE40 up to 500MHz!19:08
ZipCPUSounds like you have a 100MHz clock input, go on19:08
shaprI figured I could hack this synthesizer source to work with out of the box beaglewire19:09
shaprthen I could contribute it as an example19:09
ZipCPUSounds good, go on19:09
shaprso my question comes down to "do I just divide all the explicit clock division by five?"19:09
ZipCPUBetter to use a PLL ... you sure you don't want 50MHz?  It's a nice frequency to work at ... ?19:09
shaprfor example:
tpbTitle: FPGA-Synthesizer/pmod_out.v at master · shapr/FPGA-Synthesizer · GitHub (at
shaprwhy is 50MHz a good frequency?19:10
shaprhi FL4SHK ! How'd you end up in this nifty community?19:10
ZipCPUIt's fast, and it's got plenty of room for logic19:10
FL4SHKshapr:  ZipCPU's influence19:10
* ZipCPU grins broadly19:10
shaprgood reason!19:10
shaprFL4SHK: do you do FPGA stuff for money?19:10
FL4SHKI just got my first out-of-college job that I think will be involving that19:10
shaproh cool! So you just finished your Master's? or you went on to get a doctorate?19:11
FL4SHKjust finished my MS19:11
* ZipCPU showed FL4SHK how to use formal verification methods on his college project. He told ZipCPU it'd never have worked without the formal methods.19:11
shaprI'd like to go back and get a master's but it did take me twenty four years from start to finish for my bachelor's19:11
shaprmind you, I really *enjoy* taking college classes19:12
FL4SHKsome of mine I actually did really enjoy taking haha19:12
shaprI love learning far more than I care about grades19:12
shaprmy GPA was never impressive, but when I learn something it sticks in my head forever19:12
shaprthat's all I care about19:13
* shapr swears at pagerduty19:13
ZipCPUshapr: If you want to configure a PLL, you'll need both icepll as well as the iCE40 documentation for their PLLs19:13
shaprfor learning by others, why not just use stock BeagleWire 100MHz and modify the synthesizer to handle that?19:14
shapralso, verilog still makes me angry that I can't parameterize clocks19:14
ZipCPUYou could19:14
ZipCPUIt's not a bad idea19:14
ZipCPUOnly problem with 100MHz is ... what happens if you can't get your logic running that fast?19:14
ZipCPUJan Gray suggests, for high speed clocking, pick a clock rate and stick with it--so you might be good19:15
ZipCPUMy problem is that I started with the ZipCPU at 100MHz on an Artix-7 device ... and so all my logic references are with respect to that experience.19:15
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ZipCPUshapr: What kind of speakers do you expect to be using?  As in, what interface will they be expecting?  I2S?  PWM?19:18
shaprI have the i2s pmod from digilent that the original author used19:18
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ZipCPUWhat clock speed did he use for it?  1MHz??  That would seem rather odd.19:19
shapri2s is a digital protocol19:19
tmeissnerDoes anyone tried to build SymbiYosys from source?19:19
shaprZipCPU: pagerduty is being needy, I'll return sometime :-/19:20
tmeissnerI cannot build Avy, I get compilation error19:20
ZipCPUtmeissner: I do it all the time19:20
ZipCPUshapr: ;)19:20
tmeissnerI assume that the error results from implicit conversions which are now illegal with the latest C++ standard19:21
ZipCPUWhat machine are you building on?  Ubuntu?19:21
tmeissnererror: narrowing conversion of '2500023266u' from 'unsigned int' to 'int' inside { } [-Wnarrowing]19:22
ZipCPULet me check if I can build it (Ubuntu 16.04) ... it's been a while since I have19:22
tmeissnerI get a lot of these during compile19:22
ZipCPUThose are probably not an issue19:22
tmeissnerNot all, some are warnings, but these are errors and result in compilation abort19:22
ZipCPUWhat compiler are you using?19:26
ddrownis that gcc 8.x?19:27
ZipCPUAs in ... what version of which compiler?19:27
* ZipCPU is still using GCC 5.419:27
tmeissnerI don't know exactly, I used the apt-get line from the symbiyosys doc19:27
tmeissnerI look after the version, please wait19:27
ZipCPUTry typing "gcc -v"19:27
ZipCPUIt should show up on the last line of that output19:27
tmeissnergcc version 6.3.0 2017051619:28
* ZipCPU just upgraded his avy, is about to start building ...19:29
* shapr grumbles19:29
shaprok so19:29
shaprZipCPU: so I could just divide the clock division counts by five and it'll most likely all work?19:29
ZipCPUGenerally, you should use a PLL if at all possible for any clock adjustments19:30
shaprwhat does that mean?19:30
ZipCPUMost FPGA devices have a series of special PLL hardware blocks within them19:30
shapris the external clock of the BeagleWire not a PLL?19:30
ZipCPUNo, that's a clock19:31
ZipCPUImagine that to be an incoming square wave toggling at 100MHz19:31
shaprFL4SHK: if you ever want advice on writing Python or Haskell code, I can help :-)19:31
shaprsure, ok19:31
ZipCPUYour goal is to get some other rate ... 20MHz you said19:31
FL4SHKshapr:  well tbh I've been programming for much longer than I've been writing HDL codehaha19:31
shapryeah, different speeds for different things, yeah19:31
FL4SHKHaskell is kind of foreign to me though19:31
shaprFL4SHK: I can help!19:31
FL4SHKI've used Python enough times to be dangerous with it19:31
shaprif you want, not gonna be pushy19:31
ZipCPUWhile it is possible to do something like: always @(posedge i_100mhz_clk) o_20mhz_clk <= ... something appropriate ...19:31
ZipCPUYou are likely to have all kinds of problems doing so19:32
FL4SHKZipCPU:  isn't the "correct" answer to use a counter instead19:32
shaproh, I thought that was how clock dividers work19:32
ZipCPUAdjusting the clock speed with a PLL is recommended19:32
FL4SHKif (counter[...])19:32
FL4SHKat least in FPGA code19:32
ZipCPUFL4SHK: No.19:32
shaprthis code does the counter thing:
tpbTitle: FPGA-Synthesizer/pmod_out.v at master · shapr/FPGA-Synthesizer · GitHub (at
FL4SHKI'm not suggesting posedge counter[...]19:33
FL4SHKthat much I know you're not supposed to do19:33
ZipCPUshapr: That should work nicely for creating outgoing clocks19:33
ZipCPUI was discussing internal clocks, such as you might use in the @(posedge CLOCK) section of your code19:33
ZipCPUThe other stuff ... have at it19:33
shaprthere's a difference?19:33
shaprI thought the external clock was the same as a PLL19:34
shaprin that they're both clock signal sources19:34
FL4SHKyou definitely don't want to do @(posedge counter)19:34
FL4SHKin... synthesizeable code19:34
ZipCPUIf you use an always @(posedge something) ... use either an externally supplied clock or the output of a PLL (both will work)19:34
FL4SHKif you want a "clock divider" without using a PLL I'm pretty sure you can do if (counter[...])19:34
* ZipCPU considers sitting back and watching his apprentice teach the lesson ;)19:35
shaprFL4SHK: I've been using Python since 1996, but professionally only since 200019:35
shaprdunno if I'm an expert, but I know more than most19:35
shaprFL4SHK: ok so... what's the difference between a PLL and an external clock?19:35
shapris the difference that I can change a PLL?19:35
shapris there any functional difference?19:36
FL4SHKPLLs need an external clock19:36
shaproh they do?19:36
FL4SHKin terms of your FPGA code it probably doesn't matter which one you use?19:36
FL4SHKPLLs are like magic to me19:36
FL4SHKbut I have used them19:36
shaprso, a PLL on an FPGA needs an external clock to feed it, but then you can change the default clock speed of your entire .. something?19:36
ZipCPUFL4SHK: You didn't read my article on PLL's?  ;)19:36
ZipCPUshapr: Yes.19:37
FL4SHKIt'd be neat if I could just make a PLL out of logic but19:37
ZipCPUFL4SHK: You can ....19:37
FL4SHKIsn't that a bad idea19:37
FL4SHKI thought it was a bad idea lol19:37
shapris it?19:37
FL4SHKMaybe I'm wrong19:37
ZipCPUIn general, it is ... but some of the Xilinx hardware has some really curious and useful capabilities ... but we are getting off topic19:37
ZipCPUshapr: The basic idea is ... external clock -> (FPGA Boundary) -> PLL -> Clock at whatever rate you'd like (within reason)19:38
shaprok, so a PLL can modify an incoming external clock19:38
shaprbut you don't get many PLLs?19:39
ZipCPUIt can cause it to change phase and frequency.  Some PLL's can also output multiple clocks with known relationships to each other19:39
shaprotherwise I could use them to do clock division for me?19:39
ZipCPUNo, you don't get many at all.19:39
ZipCPUYou don't want to use a PLL to create your I2S clocks19:39
shaprhow is a PLL different from a counter that does clock division?19:39
shaprwhy not?19:39
shaprZipCPU: I swear I need to send you more money19:39
ZipCPUWhy?  Because going through the PLL introduces some amount of ns delay19:39
* ZipCPU does not object19:39
* shapr fires up patreon19:40
ZipCPUIf you are going to send data out of an FPGA, you really want to make certain all of that data transitions on the same clock interval--so it all has the same timing relationships within it19:40
ZipCPUA PLL will give you the right frequency, but will also change phase--usually undesirably--so that you nolonger maintain a known phase relationship with the incoming clock19:41
somloZipCPU, shapr: isn't the problem with wiring up your own custom PLLs that now your clock signal would be output over "data" wires rather than dedicated "clock" wires the FPGA might be distributing inside itself? (apologies for jumping in randomly like that into someone else's conversation thread :)19:41
ZipCPUHello, somlo!19:41
ZipCPUWelcome to the discussion19:41
shaprZipCPU: upgraded to "needy student" :-)19:41
ZipCPUYes, that is one of the possible problems19:41
ZipCPUAnother one has to deal with making sure the tools can properly do timing analysis on your design19:42
shaprsince I'm already asking that kind of question19:42
ZipCPUIt can be dfficult to do that with logic19:42
ZipCPUI discussed this in an article some time ago ... I just don't remember which one!  :D19:42
shapryou have so much content!19:42
ZipCPU(It wasn't the main topic of the article)19:42
shaprI'm glad you have a patreon, I don't feel as bad about asking piles of stupid questions.19:43
* ZipCPU changes the sentence structure: "You are so content" ... and likes that better19:43
ZipCPUshapr: Go on, am I helping out with your questions still?19:44
ZipCPUSo ... I have an I2S controller I built some time ago but never used19:45
shaprok, so PLL could have different phase, hm19:45
ZipCPUI got far enough along that I was at the point where I needed to configure the audio chip and ... that's where I got stuck19:45
ZipCPUApparently, a lot of audio devices want some really weird frequency: 48.192 MHz or something like that19:45
ZipCPUCreating that frequency is ... not trivial19:45
shaprI will happily mail you a digilent i2s pmod to match the one I own19:46
shaprand a beaglewire19:46
ZipCPUWould love it!19:46
shaprheck, I'll mail you a whole kit of goodies19:46
shaprbecause then I can ask noobie questions about those goodies!19:46
ZipCPUSo far, the only audio out I've done successfully has been with either PWM, or unintentional FM19:47
ZipCPU(well, intentional unintentional FM)19:47
ZipCPUIt turns out those GPIO wires can be made to "broadcast" at your favorite frequency ... :D19:47
shaproh, did you see the hackaday article yesterday?19:48
ZipCPUOne project of mine involved playing Queen on my favorite local Christian radio station19:48
ZipCPUWhich one?19:48
tpbTitle: Your USB Serial Adapter Just Became a SDR | Hackaday (at
ZipCPUNo, I hadn't seen that one ... I'll look forward to reading it19:49
tmeissnerZipCPU I've found a forum wheresome users of ArchLinux ran into the same compile error19:50
ZipCPUtmeissner: You might consider trying to build one of the other Avy branches ... you might find it builds easier, but I can't comment on whether or not it would work better19:50
tmeissnerZipCPU they fixed it by adding a option to cmake that gcc don't take these errors only as warning19:51
ZipCPUSounds like a good temporary patch19:51
tmeissnerZipCPU the master branch of avy is pretty old (2015), so maybe you're right, that one of the other branches don't have this problem19:52
ZipCPULooks like most of the work is being done in the new_quip branch19:52
ZipCPUThere's also a quip branch which appears to have been stable for half a year or so19:52
tmeissnerLet's try the new_quip  first, I'm a adventurer today :D19:53
shaprZipCPU: so your suggestion was to change the clock signal on the BeagleWire to match the 500MHz of the original board?19:55
shaprno wait...19:55
* shapr reads back19:55
ZipCPU500MHz?  What runs at 500MHz?  The example you shared had 500 kHz in it ..19:55
shaprer, I thought the incoming clock was 500MHz for the xilinx board this synthesizer was created to run on?19:56
ZipCPUNot likely, that's way too fast19:56
shapr ?19:56
tpbTitle: FPGA-Synthesizer/pmod_out.v at master · shapr/FPGA-Synthesizer · GitHub (at
ZipCPUI'm pretty sure that's a typo19:57
daveshahGiven they seem to divide by 25 to get 2MHz it must be a 50MHz clock19:58
shaproh yeh!19:58
ZipCPUThe code is broken as well ... line 39 shows a classic off-by-one error19:58
daveshahWhich is much more plausible19:58
shaprI just realized that!19:58
shaprI'm glad you two can read better than I can19:59
ZipCPUdaveshah: But they aren't creating 2MHz anywhere ... are they?  I'm only seeing kHz number19:59
daveshahWell "2000kHz"19:59
daveshahActually 1923kHz as you say19:59
ZipCPUAhh ... okay, that starts to make more sense.  I think the incoming clock though is 100MHz though19:59
ZipCPUSince they appear to be dividing the incoming clock by 52 ((25+1)*2)20:00
ZipCPU(I think that's a bug by the way--you can tell that whoever wrote this didn't formally verify it :D )20:00
daveshahIt depends if that comment refers to the frequency that block runs at or the frequency of the clock it creates20:00
daveshahI also see they have a non constant initial value for sig_tmp20:01
* shapr reads
shaprdaveshah: what does that mean?20:02
daveshahSee the initial block20:02
daveshahThe initial value is set to the sig input20:02
daveshahThis is not feasible in FPGA hardware, and wouldn't make much sense if it was20:02
shaprWhat's sig?20:03
shaprdaveshah: you have context I am missing, what does that imply?20:03
tpbTitle: FPGA-Synthesizer/pmod_out.v at master · shapr/FPGA-Synthesizer · GitHub (at
tmeissnerZipCPU new new_quip branch compiles nearly to the end, but then there is another error, it can't find some file of the boost library20:04
daveshahIn hardware this would imply sampling sig at the moment the FPGA boots to initialise sig_temp20:04
shaprand that's bad?20:04
daveshahBut FPGAs can't do that20:04
tmeissnerI will have a look, if it's somewhere else20:04
daveshahThe synthesis tool will either ignore it with a warning or error out20:04
shaprsounds like I should try to throw this codebase into yosys and then squander ZipCPU's time with noobie questions20:04
* shapr sighs20:05
* ZipCPU clones the repo20:05
shapron the good side, it seems like my question has turned into much useful information for me!20:05
* ZipCPU starts adding formal properties ...20:05
shaprdaveshah: I thought sig was passed into the module?20:06
* ZipCPU renames MCLK o_i2s_mclk, LRCLK as o_i2s_lrclk, SCLK as o_i2s_sclk, etc.20:07
* ZipCPU replaces output name with output reg name20:08
* ZipCPU adds `default_nettype none to the top20:08
daveshahshapr: yes it's an input to the module (and therefore not a constant, or at least not guaranteed to be one)20:08
* ZipCPU replaces input clk with input wire i_clk20:09
daveshahYosys will probably error out, most tools will ignore it with a warning20:09
daveshahAs synthesis tools are free to ignore initial blocks if they want too, either behaviour is arguably correct20:09
* ZipCPU replaces sig_temp <= sig; with sig_temp = 0;20:09
* ZipCPU removes "<=" from the initial block, replacing it with "="20:10
* ZipCPU notes that this code never passed a verilator -Wall test20:10
* ZipCPU finds blocking assignments where there should be non-blocking assignments ... (See MCLK = ~MCLK)20:11
* ZipCPU finds references to the (blocking assignment results) at the end of the file. These explain why he thought there was a divide by 2620:13
* ZipCPU notices a lack of a reset, and then tugs at his beard pondering20:14
somlodaveshah: prjtrellis examples ( mention a TinyFPGA Ex board with an 85k ECP5; however, the TinyFPGA EX at says it's using a LFE5U-25F (i.e., 25k). Did they have a limited-edition 85k one, or is that a typo?20:15
tpbTitle: prjtrellis/examples at master · SymbiFlow/prjtrellis · GitHub (at
somlodaveshah: nvm, I meanwhile found :)20:19
tpbTitle: TinyFPGA EX | Crowd Supply (at
shaprZipCPU: I know some of those things20:35
shaprdoes that mean you should not do <= in the initial block?20:36
ZipCPUVerilator can't handle "<=" within an initial block20:37
ZipCPUYosys can't handle "=" within a memory initialization in an initial block20:37
shaprhow would I recognize a memory initialization?20:38
shaprI should read all the ZipCPU tutorials first20:38
* ZipCPU rummages20:38
ZipCPUMemory initialization is currently discussed in my (still draft) lesson 8: Block RAM20:39
ZipCPULet me post a slide from that lesson though ..20:40
tpbTitle: Imgur: The magic of the Internet (at
ZipCPUHere's some of the rules I use to make certain the memories I create/define are inferred properly:
tpbTitle: Imgur: The magic of the Internet (at
ZipCPUI think rule #2 is perhaps the most common frustration among beginning designers using memory20:44
shaprram init seems sensible enough20:46
shaprZipCPU: if you have multiple always blocks, do they act as one?20:47
ZipCPUOfficially: No  Unofficially, it might depend by what you mean20:47
ZipCPUI typically write my designs with as many always blocks as I have variables, or just shortly less than that--mostly for cost savings20:47
shaprmostly wondering if multiple always blocks in the same module are equivalent to one always block with the same code20:48
ZipCPURoughly, yes, but it doesn't work in reverse20:48
shaprbecause ordering?20:48
ZipCPUOrdering, yes, and also references to things within the block20:49
ZipCPUThe simulator is free to pick whatever order it wants to execute the always blocks using20:49
ZipCPUThis is where blocking (=) vs non-blocking (<=) gets ugly20:49
shaprnot sure I actually like verilog20:50
ZipCPUIf you have a blocking (=) assignment in one always block, and a reference to the value in another, which will get executed first?20:50
shaprbut it's what I have20:50
ZipCPUYou'll also have problems with Verilator ... it doesn't handle blocking assignments (=) very well20:50
ZipCPUTo avoid hardware/simulation mismatch, always use the non-blocking operator (<=) within any clocked always block, and the blocking operator (=) within any combinatorial always block20:51
ZipCPU(That much was in the tutorials ... see lesson two)20:51
tmeissnerI think there are some goop papers from sunburst regarding thi problems with (non)blocking assignments20:52
ZipCPUCould be ... but I don't remember seeing any such papers20:52
ZipCPUI might need to look again--that would be valuable20:52
adamgreigwhat's the deal with always @* begin bla = 1'h0; bla = some_other_sig; end20:52
tmeissnerBut the hint of ZipCPU is best for beginners I think20:52
adamgreigodd syntax for initialise to 0 and thereafter combinatorially equal to some_other_sig?20:53
ZipCPUadamgreig: Not at all.  the first assignment will be ignored in favor of the second.20:53
tmeissnerI can remember to some Verilog 4 VHDL users course at Doulos. And this problem was  handled very at the beginning20:53
adamgreigwhere bla is "reg bla"20:53
adamgreigZipCPU: so the first assignment is meaningless?20:53
somlo"always @*" is combinational, though (always_comb in System Verilog)20:53
ZipCPUadamgreig: Yes20:54
adamgreigyea, so why would you write two blocking assignments in a combinatorial block to the same register?20:54
somloas opposed to always @(some_edge some_signal), which is where you'll want to limit yourself to nonblocking20:54
somloadamgreig: so you can have Verilog sort things out for you: bla = 0; if (something) then blah = 4'hF; else ... etc20:57
adamgreigi mean just literally "reg foo; always @* begin foo = 1'h0; foo = other_sig; end"20:57
somloyou get a default value, and if some conditions are true you might end up assigning something else -- but you'll always have assigned *something* to it20:57
somloI think that's redundant (legal, but the 1'h0 thing gets optimized out)20:58
ZipCPUHere are some good rules:
ZipCPUSee page 5 for example20:59
adamgreighmm I think the intent here is probably assigning initial values21:01
adamgreigthis is yosys-generated verilog from rtlil21:02
ZipCPUNo, I don't think so, since that wouldn't assign an initial value21:02
ZipCPUI think the intent is to make sure some value, any value, is assigned--to avoid latches21:02
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