Saturday, 2019-01-05

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phireWhat's the best way to generate a netlist with proper names on the flipflops?05:31
phireModify the proc_dff (and subsequent passes) to generate and perserve names?05:32
phirewrite some kind of post-processing script or pass that generates a name based on the output wires?05:32
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daveshahphire: imo, a fix that generated names for cells based on output wire name would be very useful09:18
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puddingpimpit seems like it would be useful if there was a traceable link from every AST node to the pass and input AST node(s) that produced it11:55
puddingpimpbut I guess that presumes that the prior AST state is stashed away somewhere11:55
puddingpimpI'm just an observer and not that familiar with yosys internals11:56
phireThe previous state is deleted on each pass11:57
puddingpimpI do know that, I'm part of the way through te yosys manual atm11:58
phirethe src attributes really should be propergated to every single generated node12:02
puddingpimpso there is the HDL AST and then the yosys AST (from what I understand) does the HDL AST from the lexer stick around in memory?12:04
phireWell, you can save out the IL at any point and load it into a new instance of yosys later12:06
puddingpimphow early/late is the AST flattened, eg. if I have 4 instances of a module A, which has two instances of module B, is module A and B optimised once each and then flattened,12:07
puddingpimpor is the whole AST flattened before any later processing12:07
phireI think the typical workflow is to run the hierarchy pass early on before optimising, which I understand flatterns the design.12:13
daveshahread_verilog does by default elaborate & simplify the AST with the default parameter set for a module (turned of with -nodefer); but keeps the AST around in case the module is encountered with a different set of parameters12:14
daveshahhierarchy will elaborate all modules as instantiated with their parameter set12:14
daveshahflattening is optional at this point, and pretty much unrelated to elaboration of the AST12:15
phireOne problem with the manual, is that it doesn't really give you much idea which passes you should be running in which order12:17
daveshahThere is a bit on this in the appnotes at the end12:18
daveshahtldr; always run hierarchy and proc before anything else12:18
phireRight now I'm trying to generate nice looking schematics of my design12:19
daveshahHave you seen
tpbTitle: GitHub - nturley/netlistsvg: draws an SVG schematic from a JSON netlist (at
phireyeah, I'm considering improving it12:20
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phireI think I actually want a "looks good in schematic form" technology library.12:24
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