Saturday, 2018-12-29

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hedgebergKitlith: freaking seriously? how many channels are you even in07:18
hedgeberganyway, hiya, got a question re: systemverilog synthesis/PnR if anyone is in07:18
hedgebergdm'ed clifford on twitter but I'm p sure he has bigger fish to fry, given 35c3 is a thing rn07:20
hedgebergso, like, figured this was the best place to ask. Question is basically just:07:21
hedgebergis enum currently supported? if so, what does it take to get yosys to play nice with it?07:22
hedgebergI could swear I remember a twitter conversation during which clifford said it was supported, but now that I'm trying yosys for the first time I'm having 0 success07:22
cr1901_modern Looks like they aren't07:32
tpbTitle: SystemVerilog enum types · Issue #248 · YosysHQ/yosys · GitHub (at
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hedgebergcr1901_modern fair enough. Any idea what it would take for someone with uh, all of 0 compiler experience to implement the enum token?08:17
hedgebergalso, while I'm at it, what's the status of supporting any of the Xilinx 7 series chips in nextpnr?08:17
cr1901_modernhedgeberg: My recommendation would be to read chapters 2 and 3 of Appel's Modern Compiler Implementation in C. It explains the theory behind lex and yacc so you (in principle) never have to impl it yourself.08:18
hedgebergI remember hearing there had been some extensive RE of the bitstream format? is there anywhere I could go to see what has been done/needs to be done?08:18
sorearso was pushed yesterday but I'm not sure how much of a step towards the eventual long-term solution it is08:18
tpbTitle: GitHub - YosysHQ/nextpnr at xc7 (at
tpbTitle: SymbiFlow (at
cr1901_modernOr Dragon Book (which is what clifford read AIUI)08:19
hedgebergo, that would make sense considering its 35c3 and therefore release time.08:19
* cr1901_modern is currently reading the LR part of Chapter 308:20
hedgebergok so I hate to be that guy, but... think I could figure it out by looking at how other tokens are handled in the compiler???08:20
sorearthe branch uses a third-party (and GPL3) tool "torc" to do some of the work08:20
cr1901_modernhedgeberg: YMMV. I'm a bit too stupid to figure it out w/o reading a book :P.08:20
daveshahYes, this basically means it uses the official databases and ISE bitgen rather than XRay08:20
hedgebergdaveshah so, its not reversed from ISE/vivado? it instead uses xilinx's own data?08:21
hedgebergfascinating, never heard of torc before.08:21
daveshahYes, Torc is intended for use by universities, etc for research08:22
daveshahThere's a more modern equivalent RapidWright for Vivado08:22
hedgebergare they.. supported by xilinx?? i find that surprising08:22
daveshahIt shouldn't be hard to move bitstream generation to use XRay FASM once XRay has IO support08:22
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daveshahI guess endorsed but not supported by Xilinx08:22
hedgebergoooh, they have some virtex IV support. nice. maybe by the time I need to use my nice virtex IV board,it wont need to be with ISE.08:24
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daveshahWith Torc you still have to use ISE for bitstream gen08:25
hedgebergoh, bleh08:25
hedgebergat least it removes the synthesizer/pnr from the loop08:25
daveshahUntil someone (mwk hopefully) does bit docs for Virtex 4 at least08:25
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daveshahHe's been looking at bitstream stuff for various Xilinx parts08:27
hedgebergngl part of me feels like its almost better to reverse than use other people's tools, but I also know thats probably not a good way of approaching this08:28
hedgebergso, I guess this is something I've always been curious about, whats the level of difference between the bitstream and then PnR output?08:29
daveshahThe PnR output is basically text describing functionality and routing08:30
cr1901_modernFor the FOSS tools, the pnr output is ascii repr of bitstream08:30
hedgebergI'm sure its clearly more complex than im assuming, but to my unfamiliar ape brain, I'd assume the pnr output and bitstream are 1-to-108:30
daveshahFor xc7 and ecp5 the PnR output is higher level but still 1 to 108:30
daveshahFor example we describe connectivity in terms of wire names08:31
daveshahThis needs to be looked up to actual bits08:31
hedgebergyeah, its like an assembler08:31
* cr1901_modern wonders how much ice40 sales will take a nosedive once the series 7 bandwagon gets rolling08:31
hedgebergI think the ice40 chips will stick around for a while08:32
hedgebergthey had a real market before OSS stuff, and they'll have a real market afterwards too08:32
sorearif everyone in this chat buys a devboard that's how many ppb of lattice's volume?08:33
daveshahI think we will keep recommending ice40 for beginners stuff for a long time too08:34
hedgeberganyway, I guess the reason im confused is that, if you can make a pnr output file where youve enabled some small set of routes/flipflops/gates/etc, and then run bitgen on it, it should be relatively simple to document how different pnr output elements correlate to bitstream?08:34
daveshahYes, that's exactly what I did for ecp5 and similar to what clifford did for xray08:35
sorearI have no idea why we're following the gcc approach of having an assembler instead of the modern-compiler approach of generating binaries and having a disassembler for debugging08:35
hedgebergand has noone done it for xc7 then?08:35
daveshahThey have08:36
sorearthe xc7 work doesn't include I/O cells yet, so it's difficult to demo08:36
daveshahIt's just a bit rough around the edges and not the best place to start developing a PnR tool with right now08:36
daveshahAnd that08:36
daveshahYou can work around the IO issue with partial reconfig, but when writing a PnR tool you want as few things as possible to debug08:37
hedgebergsorear the use of an intermediate language etc honestly makes /more/ sense re: hdl to me than it does re: machine code08:37
daveshahIn particular Eddie was very familiar with Torc and XDL because of Verilog to bitstream in the past08:37
daveshahSo it was a natural place to start08:38
hedgeberglike, in hdl you extract your state machines and your netlist, which is the perfect use for an intermediate representation imo08:38
hedgebergalso, what compilers come with decompilers? because that sounds amazing. I'd love to not have to use IDA anymore08:39
daveshahRTL ILs, the biggest thread in open source EDA, locked after 1000000 heated replies08:40
hedgebergoh so I'm not the only one with A Strong Opinion(tm) on this subject08:40
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tpbTitle: Lowlevel LLVM-like language as HDL middle layer · Issue #19 · SymbiFlow/ideas · GitHub (at
daveshahPresented without comment08:42
cr1901_modernThe OP is also a piece of work08:43
hedgeberganyway, daveshah now that im a bit more up to date, ill prolly try to mess around with implementing enum into yosys over the next couple of days. assuming i somehow manage to make it work, i guess the main question then is where would it be best to throw in some work on xc7?08:43
hedgebergworking on reversing io cells?08:43
daveshahYou could speak to digshadow about that?08:44
hedgebergalso yeah, cr1901_modern he seems like it tbh...08:44
daveshahHe doesn't seem to be in this channel. Might be work asking in #symbiflow08:44
cr1901_modernhedgeberg: No I'm not bitter that the r*dare devs quote tweeted me, why do you ask?
hedgeberganyway, why a language??? its a netlist + state machines... a low-level language seems like overkill?08:46
hedgebergand, god, f*ck the r2 devs.08:46
hedgebergI keep wanting to try r2, and every time I think of it, I remember how rude they are and continue to be.08:47
cr1901_modernThere's no alternative, I refuse to use IDA, so I handroll my own dev env from open source "smart" tools08:48
hedgebergalso, cr1901_modern I /knew/ I recognized your name, just wasnt sure from where.08:48
cr1901_modernhedgeberg: Yea, I still owe you homework :)08:48
daveshahFWIW for the netlist nextpnr uses Yosys' own JSON format08:49
hedgebergyeah, my place-of-work is an IDA shop, with a small group of binja users. Need to give binja a shot.08:49
daveshahThis is quite a good format for netlists but not so good for the earlier stages of RTL08:49
hedgebergcr1901_modern homework??08:49
cr1901_moderndaveshah: Also, RTLIL hasn't quite grown on me yet as pleasant to read, tbh08:50
cr1901_modern(as for earlier stages of RTL)08:50
soreari don't interact often with people that make me wish github had site-wide moderation08:50
hedgebergyeah, the steps before QM etc? tbh, I don't really know a good way off the top of my head to represent that step08:51
daveshahtbh I think RTLIL is intended more for internal use than as a real import or export target08:51
cr1901_modernWell, now that migen targets it (which I think is a decent idea), I have to read it08:51
cr1901_modernBtw, this is still kinda true... I'm bad at removing stuff from my todoist08:52
hedgebergpffffft dude I had forgotten about this, that was so long ago08:52
hedgebergfwiw, offer is still open08:52
cr1901_modernty :308:52
soreara Big Question which I'd like an answer to: what kind of IR is needed for a *friendly* mixed verilog/vhdl flow?08:52
hedgebergbut, yeah, i feel that :/08:52
sorearsource-to-source compilers are not the answer, unless you prefer f2c over g7708:53
cr1901_modernsorear: Sadly enough, we talked about this in j-core a few months back08:53
hedgebergsorear: idk tbh? maybe, like, some way to do large-block-netlisting?08:53
cr1901_modernthe way to get j-core to work with yosys is probably to use nvc's IR, use the llvm backend to do vhdl elaboration, and then convert to verilog08:53
soreardo the EDA vendors have any emergent standard for how vhdl/verilog mixing works?08:54
hedgebergabsolutely not08:54
cr1901_modernI can instantiate simple VHDL IP in verilog code08:55
cr1901_modernthat's the most I've ever done08:55
hedgebergfrom what I can tell, xilinx/altera(rip)/cadence/etc refuse to standardize anything wherever possible08:55
cr1901_modernsorear: (donnie_j is Jeff)08:56
hedgebergso, I figure if anything they probably all have their own way of doing this and refuse to collaborate08:56
sorearI'm sorry, why wasn't this in #j-core ?08:56
cr1901_modernBecause Jeff wasn't registered that night08:57
cr1901_modernand he was pressed for time08:57
hedgebergwhat is j-core btw?08:57
cr1901_modern(#j-core only lets registered users speak)08:57
hedgebergnew to the OSS FPGA landscape, so a lot of this escapes me08:57
cr1901_modernhedgeberg: Remember superH? Dreamcast and Saturn and 32X?08:57
cr1901_modernit's a free version of that08:57
sorearcr1901_modern: how oten does this happen, any utility in my lurking #jcore?08:58
sorearit's a … frustrating project to care about08:58
cr1901_modernsorear: In the past 2 years, that was the first time I've seen him on IRC08:58
hedgebergat the risk of sounding ignorant, whats the benefit over riscv?08:58
sorearit's developed entirely behind closed doors by a team that speaks Japanese08:58
cr1901_modern(not the first time I've talked to him)08:58
cr1901_modernhedgeberg: Better insn density08:58
cr1901_modernit uses 16-bit insns08:58
cr1901_modernall the way thru. With all it's benefits and disadvantages08:59
sorearthere is a version with a MMU.  it is not public.  the *programming documentation* for the MMU is not public.  no, it's not the same as the Hitachi SH4 MMU08:59
hedgebergooh, neat, if not maybe a bit messy.08:59
hedgebergsorear im so sorry for your loss08:59
sorearit's not my loss08:59
hedgebergsorry, im bad at jokes08:59
cr1901_modernsorear: There's nothing I can do about that. All I can do is be patient, because even if it's taking a while, I still want it to succeed08:59
hedgebergim just quipping about the fact that it sounds like a horrible project to be invested in09:00
cr1901_modernThe more free CPUs the merrier09:00
cr1901_modernThat would explain why I haven't seen you chat in a while tho09:00
sorearthe j-core project predates riscv, and they've focused on "make a small number of socs that are nice to use" over the broader-range platform questions09:01
sorearI'm there, I just don't really speak unless spoken to09:01
cr1901_modernor I'm asking a stupid question about PIC09:01
hedgebergthat sounds nice, tbh. I can appreciate that.09:01
cr1901_modernthat also seems to get your attention09:01
hedgeberganyway, ill prolly give a stab at implementing enum over the next couple of days, so if im here a lot and asking a lot of annoying questions, thats why, and also im very sorry09:02
cr1901_moderndon't be :P09:02
soreari'm not a j-core expert but I know more than I should about ELF legalese09:02
sorearso I can answer those09:02
cr1901_modernsorear: In any case, I brought up this convo b/c: If j-core ever runs on yosys, using nvc is the way it's likely to happen09:03
cr1901_modernand that might be the only way to get verilog and vhdl to "play nice"09:03
cr1901_modern(in FOSS land)09:03
sorearsh is kinda similar to thumb1; the cost of the fixed 16-bit encoding is more instructions in common cases than arm32, because you can't use any register for any inptu and output09:03
hedgebergthat or make some completely new intermediate netlisting tool that can allow for abstract modules and link them together later?09:04
hedgeberg"link", i guess, since its very much not like linking in the software sense?09:05
hedgebergidk if that sentence made sense at all i need coffee09:05
sorearcr1901_modern: see I would have assumed the hack answer was vhdl2vl09:05
cr1901_modernhedgeberg: Sorry it didn't make sense. But it's also 4am and I should be asleep09:05
sorearhedgeberg: the crux of my question above is "what is a module?  discuss"09:06
cr1901_modernsorear: vhdl2vl isn't free I don't think?09:06
sorear ?09:06
tpbTitle: vhd2vl/LICENSE at master · ldoolitt/vhd2vl · GitHub (at
cr1901_modernOh, I thought you were abbreviating vhdl2verilog09:06
cr1901_modernin any case, I know that tool now09:07
cr1901_modernj-core is too complex for it. nvc is the only free vhdl compiler that can handle j-core09:07
cr1901_modernand since I don't want to write a front end09:07
cr1901_modernI proposed bastardizing nvc to generate verilog09:07
hedgebergi should go to bed too, fwiw, but i have a headache so going to sleep would actually suck more /with/ coffee than without09:07
hedgebergno i got that backwards09:08
cr1901_modern(nvc's parser is 5000 lines. Handwritten.)09:08
hedgebergi should stop trying to talk, ill be back tmrw probably o/09:08
cr1901_modernset up a bouncer :)?09:08
cr1901_modernor just keep your client on (like I do lol)09:09
hedgebergyeah, thats the plan, i was jsut saying bye for good manners. im not logging off09:09
hedgebergone day when i finish my new home server architecture, ill resume running a znc instance09:09
hedgeberguntil then, meh, not on irc enough to bother09:09
sorearnvc versus ghdl?  the j-core tarball includes ghdl makefile bits09:14
cr1901_modernI forgot the deal w/ ghdl09:15
daveshahThere is ghdlsynth, but it only supports a small subset of functionality (less than vhdl2vl on my testing)09:18
cr1901_moderntbqh, it's probably easier to write a "competing" impl in verilog or migen and feed it to yosys lmao09:19
cr1901_modernmaybe not the MMU or multicore version09:19
cr1901_modernbut I don't need either of those for my use cases (use sh2 w/ litex)09:19
* cr1901_modern should prob go to bed for real this time and _not_ watch more anime09:23
sorear(not a reply) the only HDLs I have much knowledge of relevant to implementation are systemverilog and bluespec09:23
soreari'd like to spend time studying (n)migen, vhdl, clash, kami, etc09:24
cr1901_modernwell verilog is just boneless systemveri-09:24
cr1901_modern/me is smacked09:24
sorearIMO verilog is "what people called systemverilog prior to 2005"09:24
cr1901_modernsystemverilog is "super"-verilog09:25
sorearthis doesn't seem to be a case like C and C++ where WG11 continues to exist and continues to make new standards that are incompatible in new and exciting ways with what WG14 did09:25
sorear*WG14 and WG2109:25
cr1901_modernC seems to be... not updated that often?09:26
cr1901_modernI think there's a C20, but it's meh09:26
cr1901_modernAnd as for bluespec- not interested in Haskell, sorry09:26
sorearthere was an 11 year gap between (s)v specs so whatever09:26
cr1901_modernI just don't grok it and I don't think I ever will09:27
sorearit hasn't used haskell syntax in a decade09:27
cr1901_modernI just am going by the wiki article :)09:27
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sorearalthough bluespec's elaboration-time semantics are basically identical to haskell 98 + MultiParameterTypeClasses + FunctionalDependencies09:29
* cr1901_modern knows some of those words09:29
cr1901_modernI do fully admit that it isn't an accident formal flows like SMTv2 look like pure functional languages09:30
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sorearin which I notice that ghdl is written in Ada09:41
sorear_fitting_ but annoying09:41
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maikmertenjust finished watching the wonderful SymbiFlow talk from 35C3. Great presentation!10:47
maikmertenjust wondering if the "hostile towards Open Source" regarding Lattice is a new (active) development or the usual (?) passive "no specs for you"10:49
daveshahLattice are *not* hostile towards open source10:50
daveshahidek why that was mentioned10:50
maikmertenah, great10:50
maikmertenokay, that confused me a bit10:50
daveshahyes, particularly if you've been following @ico_TC recently..10:50
maikmertenwell, I've watched the risc-v softcpu contest, with Lattice actually spreading boards and the yosys toolchain *not* being discouraged10:52
sorearat the end mithro talked about some fpga vendors being hostile/neutral/supportive, but didn't name names for any category10:52
daveshaheven at Xilinx there are certainly individuals who are very supportive of open source  (hence rapidwright)10:54
sorearSilego/Dialog gave azonenberg bitstream documentation for the GreenPAK, which he used for yosys support a few years ago (and a separate tool "gp4par")10:54
sorearin the 90s there was a company that did gate-array ASICs layout-compatible with some Altera part, and their flow involved using Quartus to synthesize and pnr a customer design, then $company would convert the bitstream into metal masks10:56
sorearAltera sued them on the grounds that they were inciting customers to violate Altera's EULA (which only permits use to program Altera devices)10:57
sorearit's unclear how relevant this is to what we do10:57
maikmertenheh, IIRC Altera also happened to offer mask-programmed parts based on some of their FPGAs10:57
maikmerten(they don't anymore)10:57
nats`if it's like xilinx it's not mask programlmed10:59
nats`they just sell you a fpga tested with your design10:59
nats`and it's cheaper because many function can be defective but you don't care10:59
nats`(but obviously you can't use the fpga with an other design or only at your own risk)10:59
daveshahLattice had something like this at one point too (FreedomChip)11:01
daveshahI understand this also involves some kind of soft scan chain insertion during synthesis11:01
sorearMicrochip/Microsemi didn't seem especially enthusiastic about icestorm in 2016 but I have no idea what the current status is11:03
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MoeIcenowysorear: the AGM FPGA chips I recently researching recommends to use Quartus to synthesis...11:52
MoeIcenowy(although the toolchain also supports to use yosys to synthesis11:53
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sorearI saw that on twitter (and now I see you have the same nick as the person who posted there)11:55
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sorearfrom the nvc blog:12:00
sorear> But I have a question: why did you choose C instead of C++ ?12:00
sorear> Two reasons I suppose: [...]; the second is that I find it much easier to “get things done” in C – in C++ I waste time agonising which of N possible ways I should choose to implement something: in C I just write the code ;-).12:01
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sorearideally, we would have one high quality open source verilog + vhdl frontend which could be used for linting, event simulation, wire-level simulation, synthesis, and formal verification12:56
sorearwhat we have: (a) a verilog-only frontend which deliberately cuts corners (IIRC) with error messages, can be used for synthesis and formal12:57
sorear(b) verilator's frontend which does wire-level sim and linting (c) iverilog's frontend which does event simulation and linting (d) ghdl (linting and events) (e) nvc (linting and events)12:58
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cdlearydaveshah: thanks for doing the talk on project trellis at ORConf, are things at a point where a versa dev board (with the PCIex1) is a reasonable thing to get for yosys-flow-based development? (lmk if there somewhere I should have checked instead of asking in chat? :-) tia!15:15
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daveshahAs far as readily available boards go, I'd recommend the Versa-5G or the LFE5UM5G-85F-EVN15:21
daveshahThere are examples for both of these inside Trellis15:21
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cdlearydaveshah: cool, I see that now! inferring from one of these config files that it's programmed via FTDI interface like on the ice40 boards, do those expose the UART to the FPGA on those boards as well? I can't find a datasheet that shows the uart pins ATM (Ibut I'd assume so?15:46
MoeIcenowydaveshah: by the way is ECP5 programmed via JTAG or SPI?15:46
daveshahcdleary: yes, they do. The Versa connects them by default, you need to solder some 0R resistors to get it on the EVN board15:47
daveshahMoeIcenowy: it can do either, but most boards use JTAG15:47
MoeIcenowyah okay15:47
MoeIcenowyto be honest that iCE40 can only programming via SPI seems strange ;-)15:48
daveshahI think the iCE40 was supposed to have JTAG, some of the early docs mention it15:48
MoeIcenowyand to be honest I consider the FT232H programmer still too expensive ;-)15:49
daveshahmore expensive than the FPGA...15:49
daveshahyou can use an STM32 too15:49
tpbTitle: GitHub - mystorm-org/BlackIce-II: Software, Firmware and documentation for the myStorm BlackIce-II board (at
MoeIcenowyI think it's possible to use any USB2SPI, but iceprog only supports FT232H...15:50
cdlearydaveshah: I was trying to see how your fuzzer did its I/O as well to observe changed bits without perturbing the dut, trawling the code is fun, but any key pointers/hints? :-)15:50
MoeIcenowyto be honest the cheapest chip I have seen on a USB2SPI board is WCH CH551G/CH552G15:50
daveshahcdleary: The fuzzing is all based on creating a large number of bitstreams, mostly using the 'ncl' post-place-and-route-design format, with Diamond and looking for the changes in the bitstream15:51
MoeIcenowydaveshah: by the way will the fuzzing be possible without tile -> bitstream position info?15:52
MoeIcenowyThe way to generate tilegrid in prjtrellis gives out the tile position15:52
daveshahif you can manually create, e.g. a LUT, in every tile, you should be able to work out the tile offsets more or less15:52
MoeIcenowybut in prjtang TD do not give out this info15:53
cdlearydaveshah: oh I see, no need to talk to the device at all e.g. to confirm connectivity? I was thinking of it kind of like a manufacturing test where you see if bits really push from point a to point b at the end15:53
daveshahno, no hardware is involved in fuzzing15:53
daveshahconnectivity uses a mixture of the tcl api and bitstream diffing15:54
cdlearydaveshah: gotcha, makes sense now15:54
MoeIcenowyby the way mmicko found how to decrypt the TD database, but he doesn't dare to use data in it...15:55
sorearthere is 1 NC pin on (one? several?) of the ice40 packages and there has been speculation here that it's /TRESET16:08
sorearwhat's TD?16:08
MoeIcenowysorear: the tool of Anlogic FPGAs16:09
MoeIcenowyAnlogic is a Chinese FPGA company16:09
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tpw_ruleshey all. i just saw mithro's talk about symbiyosis and am interested in working with that project. i'm more familiar with altera devices so maybe i could work on them somehow? is he around here much?17:34
daveshahmithro is here, but for that kind of stuff you might be better off asking on #symbiflow17:35
tpw_rulesoh ok, i didn't see that channel in the talk. thank you17:35
sorearhave you talked to rqou yet?17:35
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sorear(did some work on MAX V)17:35
sorear(is at 35c3 rn)17:36
rqouuh, hi17:36
rqouif you're at 35c3, you can call me at 883817:36
tpw_rulesno, i'm not17:36
tpw_rulesmy only interaction so far has been twitter rumors and the talks17:38
tpw_rulesi have not so much intelligence but lots of computers and time17:39
qu1j0t3haha, i have little intelligence or time, but plenty of computers17:40
tpw_ruleswell i'll probably come back when the c3 business has died down a little. i would be interested in talking to rqou later17:44
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maikmertenMoeIcenowy, these AGM chips look interesting18:03
maikmertena bit confused how they apparently (?) can recommend Quartus18:03
sorearonly for synthesis right?18:04
maikmertenare those hardware clones, or do they "only" borrow certain parts of synthesis and transform this to whatever they actually implemented?18:04
daveshahAs far as I know only synthesis18:04
daveshahThey aren't bitstream compatible or anything18:05
maikmertenah, good for them, I guess18:05
maikmerten(albeit perhaps still not good for their users, Quartus EULA and whatnot - but then again if they also have yosys...)18:06
daveshahAltera have sued in the past, too18:08
tpbTitle: How Bad Can It Be? Penalties Under the SCPA | Revision Legal (at
sorearlet's get rid of any qor difference ;)18:08
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sorearcr1901_modern: what are your CPI and resource utilization targets.  actually what would you be doing with sh+litex18:17
cr1901_modernCPI of 1, fit very comfortably on up5k. Could serve as a micropython target for fomu/tinyfpga18:24
sorearmicropython already supports or1k and riscv I think?18:26
sorearaverage CPI 1 is … beyond what j-core can do I think18:28
cr1901_modernor1k is never going to fit onto up5k18:29
maikmertenI think in the risc-v softcpu contest there were compact ~1 CPI designs18:29
cr1901_modernwell mor1k anyway18:29
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cr1901_modernsorear: By CPI of 1, I simply mean "classic RISC pipeline"18:30
cr1901_modernit's the theoretical limit, I'm guessing the actual CPI in practice will be 0.7-0.8?18:30
cr1901_modernerr, whoops18:30
tpbTitle: GitHub - SpinalHDL/VexRiscvSoftcoreContest2018 (at
maikmerten(classical RISC pipeline)18:30
cr1901_modern1/0.7 to 1/0.818:31
sorearnot counting cache misses, probably around there, maybe 1/0.918:31
sorearI don't have a great feel for the fraction of fun instructions like postincremnt18:31
sorearthis spreadsheet is suprisingly comprehensible18:33
sorearconcerned by the PC = INC / HOLD column though18:34
cr1901_modernvexriscv currently does run on litex, but at present there's issues with wishbone conversion layer. Minimum 1193 logic cells is nice though (compared to ~1500 for anything litex uses for up5k right now).18:35
sorear*puts 2 and 2 together* I am skeptical j-core will fit18:39
soreartheir target board is a 9K LUT6 s6, and it probably hasn't come into contact with ice40's "no distributed RAM" quirk18:40
cr1901_modernWell, I can still humor a competing impl :P18:53
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sorear(see topic if you're unclear on what this is)19:43
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ZipCPUsorear: What's wrong with a S6/LX9?  It can be done if you use your resources wisely.  I managed to put a multi-tasking O/S on one of those even.22:37
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sorearZipCPU: nothing.  cr1901_modern wants to take a design that's proven on xc6slx9 and run it on ice40up5k, but the latter is about a third the size22:44
ZipCPUOoohhh .... okay.  That makes more sense of the conversation22:44
sorear(i'm assuming s6 is also a LUT6 family and applying the 1.4x fudge factor)22:45
cr1901_modernsorear: I'm pretty sure that's the whole soc though, not just the CPU core22:45
ZipCPUOne of the tricks to getting the S6SoC I built running was being *VERY* judicious with how the peripherals were built ..22:45
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