Friday, 2018-12-21

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key2how can one generates verilog without comments ?18:18
daveshahkey2: I don't think there is an option for this. The only comment I see is the first "generated by" line, which you could strip out with `sed 1d`18:24
daveshahAre you sure you don't mean the attributes?18:24
key2yeah i mean those attr (* src = "/x/x/x/" *)18:25
daveshahUse `write_verilog -noattr`18:25
daveshahor, alternately `write_verilog -attr2comment` if you want to turn them into real comments (/**/)18:25
key2I see18:26
key2but then would I lose other usefull attribute ?18:26
daveshahIt is fairly rare for attributes to affect how a design functions, normally they are just useful info like `src` or tool-internal hints. If you don't have any (* *)s in your Verilog input, chances are you don't need any in the output either18:27
daveshahout of curiosity, what tool are you feeding this verilog into?18:27
key2vivado or verilator18:28
daveshahI don't think either of those will have any problem with attributes18:28
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key2working wiht nMigen, generating rtlil and converting to verilog18:29
daveshahOh awesome! I'm really excited about nMigen18:30
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key2just generated my riscv with it18:32
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janrinzenext-pnr is a great addition to the icestorm/yosys environment. kudos to all involved.18:54
janrinzeas a small test has already shown me it can produce up to 20% faster stable clock for my SoC design. Nice!18:55
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key2Someonas has some experience about generating verilog code for verilator ?19:50
key2I wonder if there are any kind of optimisation that are needed19:50
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ZipCPUkey2: I use Verilator all the time20:24
ZipCPUI don't generate my Verilog code explicitly for verilator though--it's just my normal Verilog code but with one exception20:25
ZipCPUFirst, I always use the -Wall option.  It provides a basic lint capability, and *SO* many bugs right there20:25
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ZipCPUThe problem with -Wall is that it also finds wires that you might not be using within your design--things you want kept there, but that Verilator properly discovers you aren't using20:25
ZipCPUFor these, I surround them with comments such as // Verilator lint_off UNUSED20:26
ZipCPUand again // Verilator lint_on UNUSED20:26
ZipCPUThird: I don't place any hardware specific code in my Verilator sections.  To do this, I place all of the Verilator synthesizable code in a subset of my design I call main.v, which is a submodule of toplevel.v.  Any thing that isn't Verilator compatible doesn't go in main.v but in toplevel.v or another submodule of it.20:27
ZipCPUAn example of such would be a PLL.  Verilator doesn't generate PLL's, so these would go in the toplevel20:28
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key2ZipCPU: I know, currently I'm testing a generation of verilog from rtlil20:58
ZipCPUOk, cool, how's it working out for you?20:58
ZipCPUI have a project, btw, that does just that ... generates verilog from a bit stream which is then run into Verilator20:59
key2well the thing is, we are testing nMigen currently20:59
ZipCPUGo on20:59
key2which generates rtlil20:59
key2I was wondering for example what you do with memrd and memwr privimives21:00
ZipCPUWow, all the way down to rtlil within migen?  Is it using yosys internally at all?21:00
key2ZipCPU: nMigen is the next migen21:00
key2I sponsored whitequarks to write it21:00
ZipCPUNice, go on21:00
key2yeah in fact it will generates rtlil21:00
key2instead of writing the verilog alla migen21:00
key2what kind of verilog do you use with verilator when using code generated from yosys ?21:01
ZipCPUYour memrd and memwr primitives ... do they have Verilog equivalents?  (They should, right?)21:01
ZipCPUYou are welcome to examine the project:
tpbTitle: GitHub - ZipCPU/cputest-harness: A simulation test harness, containing serial port, QSPI flash, and an output done I/O--just provide the CPU (at
ZipCPUThe guts are found in the primary makefile21:02
ZipCPUBasically, there's a cell simulator for the iCE40 that I was able to include to create a complete Verilator based project21:03
key2always @(posedge clk_i) x <= (y)? 1'bz : m;21:03
key2this kinda thing doesn't wokr with verilator in fact21:03
ZipCPUIt sort of does, but only at the top level.21:03
ZipCPUI've used that with success before.  I just don't know the limits of how far it can be made to work.21:03
ZipCPUOr ... maybe I've only used: assign x = (y) ? 1'bz : m; /// not sure21:04
ZipCPUI know I've used one of the two successfully, and it surprised me when I did21:04
ZipCPUYou can generate the posedge clk_i one from the assign one21:05
ZipCPUalways @(posedge clk_i) begin r_i <= y; r_x <= x; end  assign x = (r_y) ? 1'bz : r_x;21:05
key2%Error: /home/xxx/src/litex/litex/soc/cores/cpu/minerva/verilog/minerva.v:4235: Unsupported tristate construct (not in propagation graph): VARREF 'finst_pc$94'21:08
ZipCPUWhich version of Verilator?21:11
ZipCPUIs that the github version?21:11
ZipCPUI mean, raw git version?21:11
* ZipCPU is shooting in the dark21:12
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key2probably yes21:13
ZipCPUI know that there are times when it helps to create an always @(*) block to replace several assign statements21:14
ZipCPUBut, not sure if this helps either21:14
* ZipCPU is still shooting in the dark21:14
tpbTitle: debian Pastezone (at
ZipCPUYou only want one of those bits to be a 'z'?21:15
ZipCPUIf so, that's probably the problem21:16
ZipCPUVerilator is word based, and doesn't handle bit level operations all that well.  Try this:21:16
ZipCPUalways @(*) begin finst_pc94$next[30] = (rst) ? 1'bz : _144_[30]; finst_whatever[29:0] = 1 : _144_[29:0];21:16
ZipCPUOh, and don't forget the "end" on the "end" of that :)21:17
key2ha i found smth21:24
key2works now21:24
ZipCPUCool!  What was it?21:24
key2well i was getting the z because i was converting from 30 to 31 bits21:24
key2therefor, nMigen filled it with a z21:25
ZipCPUz doesn't seem like the right value to fill something with21:25
key2now I forced a concatenation21:25
ZipCPUWouldn't you rather fill it with x?21:25
daveshahYeah, x would make more sense21:25
daveshahz is tristate and should really only be used for IO pins imo21:25
ZipCPU^ +121:25
daveshahx is undefined and any synthesis tool will optimise it as a don't care21:26
key2could also x be used instead of z ?21:26
daveshahIt should be used instead of z21:26
key2on top level21:26
key2on io pins21:26
ZipCPUNo.  'z' is a tristate, 'x' is an undefined21:26
key2i see21:26
key2so thats a bug in nMigen21:26
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ZipCPUActually, let me be clearer: 'z' is high impedence, as used within a tristate.  'z' by itself isn't tristate21:27
key2it's yosys that added it21:32
key2as my rtlil didn't have this :)21:32
ZipCPUI thought you said you weren't using yosys?21:33
key2i am21:33
key2nMigen -> rtlil -> yosys -> verilog -> verilator21:33
ZipCPUJust to convert RTLIL to Verilog after nMigen creates the RTLIL?21:33
daveshahThis sounds a bit like a Yosys issue. I feel like a z in this context, even if strictly legal, is going to cause issues21:33
ZipCPUOh, okay21:33
ZipCPUdaveshah: Do you know where yosys might be adding a 'z' to RTL?21:35
daveshahMaybe if something is disconnected?21:35
ZipCPUkey2: This was a data range issue, right?  Where you were going from a 30 bit register to a 31 bit register?21:35
key2in this case, it's when you take a signal of 31 bits let say, and give it a 30 bit value21:36
key2it filled it with a z21:36
key2and verilator didnt like it21:36
ZipCPUIn Verilog, it should propagate the high order bit.  Not sure of the semantics of RTLIL21:36
janrinzein Verilog the top bit would be undefined and thus z.21:37
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ZipCPUI just looked this up the other day.  If you are assigning an N bit literal to an N+1 bit value, if the Nth bit is a z or an x, it propagates into the N+1th bit21:38
ZipCPUIf it's a 1 or 0, and the value is unsigned, it propagates up as a zero21:38
ZipCPUNothing gets left on the floor as undefined--unless you make it so21:38
janrinzesign extension is possible with signed values21:38
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key2in fact the value is a negative value21:41
key2that might explain21:41
ZipCPUConverting a set value (the sign bit) to a z sounds like a bug21:42
janrinzeif there is no initial value for the destination this may very well happen.21:44
janrinzewire [4:0] A ; reg [3:0] B=0; assign A=B; .. what is A[4] supposed to be?21:45
ZipCPUI've been programming "C" too long that the answer is too obvious.  A[4] is "supposed" to be a zero.21:46
* ZipCPU 's mind will be blown if it isn't supposed to be a zero21:46
janrinzein any case it's not C but Verilog and each bit is just a wire. A[4] is not connected to anything.21:47
key2so should it be z or x ?21:49
ZipCPUIf it's internal, it should be an x21:49
ZipCPU(or a zero ... I'm still looking that up)21:50
ZipCPUI think I found the rule in the 2012 SV standard21:51
* ZipCPU is taking a screenshot to share21:52
janrinzewhen doing arithmetic it will be different and verilog assumes that for example reg [4:0] A; reg [3:0] B; reg [3:0] C; always @* begin A = B + C; end  will get the overflow of the addition in A[4].21:52
ZipCPUYes.  That's special tho21:52
tpbTitle: Imgur: The magic of the Internet (at
janrinzeSV != Verilog.. it's a bit of a headache to get to grasp that..21:53
ZipCPUAre you suggesting I should look for another standard?21:54
daveshahI think Verilog is the same here21:54
* ZipCPU switches to 1364-200521:54
janrinzeSo what would A=B&C; result into? sign extension?21:55
ZipCPU"If a signed operand is to be resized to a larger signed width and the value of the sign bit is 'x', the resulting value shall be bit-filled with xs.  If the sign bit of the value is z, then the resulting value shall be bit-filled with zs.  If any bit of a signed value is x or z, then any nonlogical operation involving the value shall result in the entire resultant value being an x and the type consistent with the expression's21:56
ZipCPUtype" ... not quite it21:56
key2what verilog version does yosys output ?21:57
ZipCPUI think it's supposed to be 2005.  daveshah, can you correct me on this?21:57
* ZipCPU waits to be corrected21:58
daveshahI think that's correct too21:58
daveshahYosys in general is Verilog 200521:58
daveshahPossibly with a few SV extensions like assert and assume, if those are written21:58
ZipCPUOk, I found the issue in the 2005 std.  It's not nearly as clear, but I can share a snapshot21:59
ZipCPUHere's all I can find in 2005 related to the issue:
tpbTitle: Imgur: The magic of the Internet (at
daveshah It's the line above that's relevant22:02
daveshahIf needed, extend the size of the right-hand side, performing sign extension if, and only if, the type22:03
daveshahof the right-hand side is signed.22:03
ZipCPUWell, sort of ... it doesn't say to use zero extension if the value isn't signed--which I think it should say22:03
daveshahI think that's what it implies22:04
daveshahI don't think SV and V differ on anything that fundamental22:04
ZipCPUThe later standard was clearer, which was why I liked it22:04
janrinzeoh, daveshah, thanks for the quick fixes.22:05
janrinzeit looks like next-npr is a lot better than arachnepnr.22:06
janrinzeopps next-pnr22:06
ZipCPUOh, dear ... and I thought NPR was bad.  Are we now switching to discussing political topics?22:07
ZipCPUOh, ok22:07
daveshahno problem, thanks for the good quality issues :)22:08
janrinzedaveshah: I orered a up5k eval board so i can test that too. Been only using yosys with the hx8k boards like icoboard and such.22:12
janrinzeZipCPU: your SoC has libraries for reading SDcard FAT and such?22:13
ZipCPUNo.  I never got as far as processing the FAT of an SDcard.  I got far enough along that I can read and write raw sectors though.22:13
janrinzeraw sectors is a good start, i guess.22:14
janrinzeI should give that a try soon.22:14
ZipCPUAlso, I only did SPI mode.  There is a full SD-SPI simulator, and you can try working with it at
tpbTitle: GitHub - ZipCPU/zbasic: A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems (at
janrinzeyes, SPI mode seems sufficient for my initial goals22:15
ZipCPUThe file exercises it to prove that it works22:15
tpbTitle: zbasic/sdtest.c at master · ZipCPU/zbasic · GitHub (at
ZipCPUThe documentation for the SDSPI core, though, is found with the core itself:
tpbTitle: GitHub - ZipCPU/sdspi: SD-Card controller, using a SPI interface that is (optionally) shared (at
ZipCPUAlso, there's an open source FAT library that (should) make working with the core as is really easy--I just haven't tried it yet22:17
ZipCPUdaveshah: Yosys seems to be optimizing nearly my whole design away.  Any suggestions about the process to find and fix that?22:18
daveshahNothing beyond the usual trawling through logs, really22:18
janrinzei have SPI for the flash memory, so i probably could wrap a simple memory mapped I/O for that like you have done.22:19
daveshahI would expect your lint process to catch most issues though22:19
ZipCPUSo would I.  It hasn't22:19
ZipCPUjanrinze: I also have a similar QSPI flash core as well, that treats the flash memory as a bus peripheral22:20
ZipCPUIt's designed to be a "universal" core, but the first chip I tested it on needed some "special" modifications.  :D22:20
tpbTitle: qspiflash/qflexpress.v at master · ZipCPU/qspiflash · GitHub (at
janrinzeI read that people now want SPI accessed SRAM.. not sure if that's my cup-o-tea..22:22
ZipCPUHave you read about HyperRAM yet?22:22
janrinzeI think it probably only matches sytems with cache well.22:22
janrinzeor graphics buffers..22:23
ZipCPUYou mean, the SPI accessed SRAM?22:24
janrinzeor any other HyperRam that can do burst blocks but not do random access that well..22:25
ZipCPUIt's faster than a DDR3 SDRAM at random access22:26
ZipCPUdaveshah: I think I found the problem.  Initially, I was holding the system in reset.  Then, I misinterpreted yosys' "Removing unused module" statements22:27
janrinzeZipCPU: i have not seen any throughput numbers of random-access on HyperRam. DDR3 is quite slow with that indeed.22:31
ZipCPUjanrinze: If you get file access, vice sector access, running with SDSPI please let me know.  I'd love to share in the excitement. ;)22:32
janrinzeZipCPU: will do. I have limited time for my pet projects but hope to find some time during Christmas holidays.22:33
ZipCPUYeah, you and me both22:33
ZipCPUI keep trying to blog about my I-cache implementation, and everytime it's just a bit beyond me22:34
ZipCPUPerhaps I can get that done over the holidays as well22:34
janrinzei did a I-cache in software for an ARM emulator, helped me a lot with understanding the performance in respect to caching strategies and size.22:40
ZipCPUIt's been trying to explain the performance aspect that's given me the biggest struggle so far22:41
janrinzeperhaps i can convert it to verilog some day. would be nice to test it. Also cache replacement strategies can be very complex22:41
ZipCPUThe good news is that the basic formal contract is easy to express--it only takes three properties.22:42
ZipCPUThe bad news is ... it can still be a pain to get it to pass.22:42
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janrinzeZipCPU: what type of cache startegy is your i-cache?22:43
* ZipCPU has 39 assertions within his cache, others within the WB property file22:43
ZipCPUIt was easiest22:43
janrinzehow many number of 'ways'?22:44
ZipCPU1-way (i.e. direct mapped). Going from direct-mapped to N-way shouldn't be that much extra work.22:44
janrinzehmm.. direct mapped means only one block is in cache and a cache miss does stall a lot?22:45
ZipCPUDirect mapped means that for any particular cache line, the line can be described with only one tag22:45
ZipCPUDoes it miss and stall a lot?  According to H&P that depends upon the size of the cache22:45
ZipCPUH&P also recommends running with a line size of ~8 instructions or so.  I was using ~64 before, so I'm expecting a speed up in the near future due to this change of configuration22:46
ZipCPUdaveshah: Is there a way to specify a clock speed in the pcf file?23:02
ZipCPUNvm ... found what I needed in the documentation23:04
janrinzeZipCPU: does the cache use phys or virt address? or perhaps there is no MMU?23:09
ZipCPUWhile I have an MMU, I haven't yet integrated it.  So ... I suppose I might as well not have it23:09
janrinzeI found the old code and it handles the virt to phys translation as well.23:10
ZipCPUI didn't want to "pollute" the CPU with the MMU, since the purpose of the CPU was to be "low-logic".  This means that the default I-cache doesn't know about the MMU.  I'm trying to figure out how to maintain that, but reality means I'll need to modify the I-cache somewhat to support the MMU23:12
janrinzeah, i see. was tinkering with MMU the other day but it also requires a lot of software to handle and keep track of that. the sw is mainly simplistic stuff without a real OS so the MMU was getting in the way. Only graphics memory has a simple mapping for triple buffering for now.23:12
janrinzeif the I-cache lines can be invalidated from the MMU (when MMU gets new mappings) then it is possible to cache virtual addresses.23:14
ZipCPUThere was another optimization you could make, having to do with the fact that the cache line size would always be smaller than the page size23:15
ZipCPUNot remembering it now tho23:15
janrinzedepends a bit on the indexing scheme, if the index scheme spans a page then each page change invalidates all cache lines with the tag for that page.23:18
janrinzeif the index scheme is bigger then only the lines that can map to that page will require tag test and appropriate invalidation if necessary.23:20

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