Sunday, 2018-12-16

*** tpb has joined #yosys00:00
*** pie__ has quit IRC00:45
*** pie__ has joined #yosys00:45
*** FL4SHK has joined #yosys01:23
*** rohitksingh has quit IRC01:39
*** rohitksingh has joined #yosys01:40
*** leviathanch has joined #yosys02:39
*** _whitelogger has quit IRC03:45
*** _whitelogger has joined #yosys03:47
*** seldridge has joined #yosys04:21
*** seldridge has quit IRC04:35
*** pie___ has joined #yosys05:51
*** pie__ has quit IRC05:54
*** emeb_mac has quit IRC06:35
*** _whitelogger has quit IRC06:46
*** _whitelogger has joined #yosys07:17
*** s_frit has quit IRC07:59
*** s_frit has joined #yosys08:00
*** dys has quit IRC08:50
*** dys has joined #yosys09:20
*** _whitelogger has quit IRC09:30
*** _whitelogger has joined #yosys09:32
*** leviathanch has quit IRC11:30
*** leviathanch has joined #yosys11:31
*** _whitelogger has quit IRC13:27
*** _whitelogger has joined #yosys13:29
*** develonepi3 has quit IRC13:33
*** develonepi3 has joined #yosys13:38
*** pie__ has joined #yosys13:39
*** pie___ has quit IRC13:40
*** rohitksingh has quit IRC13:58
swetlandis there some reliable way of preventing yosys from obliterating specific signal names?14:20
swetlandI'd love for my clocks to somehow survive so I can meaningfully designate them to nextpnr14:20
*** lutsabound has joined #yosys14:28
swetlandhmm. maybe it's nextpnr.  I'm seeing the entities I want to refer to in the json file yosys produces14:42
daveshahI think the problem is that Yosys uses multiple names for a net and nextpnr just picks the first one arbitrarily15:17
daveshahI'm contemplating  a rewrite the JSON import soon anyway to support hierarchical designs, so I'll leave this for now though15:18
daveshahEventually we probably want some system for net aliases15:18
*** emeb_mac has joined #yosys15:29
*** pie___ has joined #yosys15:52
*** pie__ has quit IRC15:53
* swetland nods16:16
swetlandlooking at the json file, it seems nets are just numbered and referenced from any number of entities16:18
swetlandone could imagine both tracking all the names (as aliases) for the sake of being able to refer to them, but also maybe prioritizing names that came from the original verilog over synthetic ones when picking one for display. that, I suppose would require yosys to flag "true" or "original" names as such16:19
*** leviathanch has quit IRC16:26
daveshahIMO a quick solution would be to pick the name with the fewest dollars; fewest dots; ties broken alphabetically16:33
tpbTitle: json: Prefer higher level net names when a net has multiple names by daveshah1 · Pull Request #182 · YosysHQ/nextpnr · GitHub (at
swetlandahaha you are too fast16:58
swetlandI just found the spot where the net name is always overwritten by the most recent import of that netid16:58
daveshahI still want to do a proper implementation with aliases at some point16:58
swetlandInfo: Max frequency for clock  'system.clk12m': 15.83 MHz (PASS at 12.00 MHz)17:08
swetlandInfo: Max frequency for clock 'phy_refclk_glb': 60.12 MHz (PASS at 50.00 MHz)17:08
swetlandInfo: Max frequency for clock   'hdmi_clk_src': 37.09 MHz (PASS at 12.00 MHz)17:08
swetlandyeah that counts as a quality of life improvement17:08
swetlandit's not perfect -- ideally I'd specify system.clk25m rather than hdmi_clk_src, but it's much more sensible and at least will be consistent now from build to build provided I don't rename things17:09
daveshahYeah, consistency was the main point atm17:11
*** rohitksingh has joined #yosys17:45
*** ouznext has joined #yosys17:47
*** ouznext is now known as adumont17:47
adumontHi, I have a project that runs automated builds every week in  travis ci (test, simulation, synthesis, pnr...) with the latest versions of the icestorm toolchain (built from source). Today the project has failed to PNR.  Here is the log:
tpbTitle: Travis CI - Test and Deploy Your Code with Confidence (at
adumontarachne-pnr fails with builddir/alhambra/top.blif:30: fatal error: invalid formal-actual17:51
adumontSince last week build which was successfull, arachne-pnr is at the same commit, so it's not the culprit.17:52
adumontLatest build was done with yosys commit 47a5dfdaa4bd7d400c6e3d58476de80904df460d, it was OK. No error.17:52
adumontToday at yosys commit ddff75b60ab6b29bbc8425c7f5ac2e6ebbbf32a6 it fails with that error.17:53
adumontI'm running a git bisect run right now, which will hopefully find the commit in yosys that make my project fail to run the PNR step.17:54
*** rohitksingh has quit IRC17:54
adumontI'm wondering though, is it a problem on my end in my project? Is it that yosys now "generate" something new in the blif file that latest arachne-pnr stil doesn't understand?17:54
* adumont "Bisecting: 3 revisions left to test after this (roughly 2 steps)"17:55
daveshahadumont: Can you post the blif file causing the problems?18:27
*** pie___ has quit IRC18:33
*** pie__ has joined #yosys18:33
adumont@daveshah: here's the faulty blif
daveshahOh, I see18:34
daveshahI'll get clifford to revert the commit that broke that18:34
daveshahA change I made occasionally adds spaces to names which breaks blif18:37
*** seldridge has joined #yosys18:39
adumont@daveshah: ok thanks :). just opened issue 743 if you wan't to follow up on it on github. Thanks again :-D18:47
tpbTitle: fatal error: invalid formal-actual when running arachne-pnr · Issue #743 · YosysHQ/yosys · GitHub (at
*** emeb_mac has quit IRC18:47
*** develonepi3 has quit IRC19:30
*** adumont has quit IRC19:35
mrsteveman1Is $readmemb() expected to work with a single-bit memory? e.g. "reg [0:0] framebuffer [0:8191]", either with or without the [0:0]19:36
mrsteveman1I'm pre-initializing an OLED framebuffer, it works in Lattice Diamond but Yosys says "Failed to evaluate system function `\$readmemb' with non-memory 2nd argument"19:37
mrsteveman1perhaps it's really a difference in what can be synthesized for an ice40 vs a machxo2?19:50
daveshahmrsteveman1: this sounds like a possible Yosys issue. Could you put your code somewhere?20:06
*** Laksen has joined #yosys20:10
mrsteveman1daveshah actually looks like this is a false alarm, sorry! It was a typo in the readmemb() line, I just caught it :O20:16
mrsteveman1it was working on machxo2 because there's an ifdef for it containing a separate readmemb line (different relative path), without the typo in the memory name20:23
mrsteveman1thank you though :)20:23
*** FL4SHK has quit IRC20:34
*** FL4SHK has joined #yosys21:14
*** dys has quit IRC21:18
*** dys has joined #yosys21:31
*** seldridge has quit IRC23:19
*** Laksen has quit IRC23:52

Generated by 2.13.1 by Marius Gedminas - find it at!