Monday, 2018-12-10

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tecepehi, guys. yosys just came to my sight and i'm very impressed with your work. congratulations.02:07
tecepedo you know the FLAVIA project? (Free Logic Array via...)02:08
tecepeI was wondering if I wold be able to synthesize verilog code to that kind of architecture02:09
tecepethank you very much for any suggestions =) i'm kind of lost on how to start02:10
* ZipCPU googles FLAVIA02:52
* ZipCPU finds Offic coffee machines, mars drinks, and amazon page for a flavia creation 150 brewer ...02:53
tecepe ZipCPU: google for flavia free logic array02:56
tecepeit is a very simple fpga implementation02:57
tecepeit emulates an fpga in an fpga02:57
ZipCPUI had heard about something like this, but lost the link a long time ago02:59
ZipCPUIt was sort of a "java byte code" for FPGAs sort of thing--something that could run on all FPGA's03:00
ZipCPULast I heard, it wasn't very efficient at all03:00
ZipCPUDo you have any idea how efficient flavia is?03:00
tecepeIt is not efficient03:01
ZipCPUGot it.  Okay.  Yosys is about as good as the device itself, although nextpnr isn't quite as good as the device is capable of03:02
tecepeBiggest problem is to provide access to io pins, where you need to multiplex everything to the cell03:02
tecepeto be honest, i'm not worried at all about the efficiency03:02
ZipCPUWhat are you concerned with then?03:03
tecepei just wanted to put this path together, but i don't know how to start03:03
tecepei imagine i have to "teach" yosys how to deal with that architecture, right?03:04
ZipCPUHmm ... Okay, good question.  I know more of how to use the tools than how to build with them03:04
ZipCPUYes, you would need to implement your own back end03:04
ZipCPUMany backends have already been written03:04
ZipCPUCheck out the technologymap (IIRC) directory of the yosys repo03:04
ZipCPUYou should be able to find examples of what you need within there.03:05
tecepeok, i think i was in the right path. i just was not able to find much info about this step03:05
ZipCPUPerhaps the best info would be from those who have done it03:05
tecepeI'll check that directory, thank you, this is already a good start =)03:06
ZipCPUrqou: Were you the one who had done the coolrunner2 implementation?03:06
tecepeOf course, if people that implemented those backend are around, it would be very helpful =)03:06
ZipCPUdaveshah has been working on an ecp5 implementation.  He's on European time, so you'll have to wait for his morning before chatting with hi03:07
* ZipCPU is sadly not one of them03:07
ZipCPUThere's two problems though that you will need to work out: 1) The yosys back end, and 2) a place and route back end03:07
tecepenp, i'm glad you stepped in =)03:07
ZipCPUMost of the yosys team has been working on nextpnr, so you'll find backends for ice40 and ecp5 these days03:08
* tecepe is looking at that directory03:08
ZipCPUThe yosys directory you need is the techlibs directory03:08
ZipCPUThere's support within there for Altera/Intel, coolrunner2, easic (an ASIC flow), ecp5, gowin, greenpak4, ice40, intel, sf2, and xilinx03:09
ZipCPUI'm familiar with only some of those---mostly the ice40s03:09
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tecepethat is great info03:10
tecepethank you03:10
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tecepenextpnr is a new place and route tool?03:13
tecepei have heard about arachne-pnr03:13
q3karachne was developed as an ice40-specific pnr03:13
tecepesorry, this world outside of vendor tools is pretty new for me03:13
q3knextpnr is a new tool that's portable across multiple architectures03:13
q3kit has feature parity with arachne for ice40, and in progress support for ecp503:14
q3kalso a python-defined 'generic' architecture for experimentation03:14
q3kalso it has a cute qt gui03:14
q3kand is timing driven (that's important :))03:15
tecepewow, sounds fantastic03:15
tecepeyou guys have been busy =)03:15
q3kmostly clifford and daveshah ^^03:16
tecepehow does this "python-defined generic" architecture work?03:16
q3kso every architecture backend currently defines what an architecture is to the core of nextpnr03:17
q3kby defining available Bels (basic elements, ie. physical blocks onto which Cells can be placed)03:17
q3kPips (programmable inter..something point, ie. programmable switches)03:18
q3kand static Wires that connect Pips and Bels03:18
q3kfor ice40 and ecp5 these are defined in C++ as a bunch of iterators and access functions (ie. letting the nextpnr core know what Bels exist, what Wires do these Bels connect to, etc.)03:19
q3kfor the generic architecture, it starts with an empty definition of all of these in a bunch of hashmaps, and exposes a Python API to modify the architecture (add bels, pips, wires)03:19
q3kso you would write Python code that populates all the architecture elements in the architecture, and then tell nextpnr to get to work03:20
q3kyou might want to read
tpbTitle: nextpnr/ at master · YosysHQ/nextpnr · GitHub (at
tecepeit seems to ease development03:20
q3kwhich is the documentation of the arch api expected to be provided by architectures to the nextpnr core03:20
tecepei'll take a look03:21
q3kthe 'generic' architecture is mostly for experimentation03:21
q3kas it keeps all architecture non-deduplicated in memory, it's quite heavy03:21
q3kso you wouldn't want to take a 7-series architecture model and implement PnRing it via the generic architecture :)03:21
tecepevery interesting work03:24
tecepeok, so in this case, as arachne is focused in ice40, if i want to have a pnr tool for the flavia architecture, i'd need to work with nextpnr03:25
tecepei just saw the picture in the nextpnr gui in the repository, it is very cute =)03:28
tecepehaha i can say that a new world opened to me today =)03:32
tecepethank you very much, guys. it was interesting.03:33
tecepei've to go now. talk to you another time03:34
q3ki need to head to sleep as well03:34
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tecepegood that nextpnr is already creating documentation:
tpbTitle: nextpnr/ at master · YosysHQ/nextpnr · GitHub (at
tecepeso much good info... just discovered VTR03:38
tecepewell, good night guys03:44
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ZipCPUHey, this is cool: I just adjusted how I was going about the formal verification of the ZipCPU.  By checking the current state instead of transitions between states, I can now verify the CPU in less than 15 steps--vs 18 (or more) before15:49
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ZipCPUI'm current working with the ZipCPU+data cache, and I can verify the two together in only 10 steps15:50
ZipCPUThat's a full proof: BMC+Induction too15:50
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jerZipCPU, cool19:33
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