Saturday, 2018-12-08

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CerpinWon't waste too much of anyone's time on this since it's probably a simple error, but: PLL usage procedure shouldn't change between lp8k and hx8k, or between arachne/next, correct?18:58
Cerpin(I have something that's been working fine for my HX8K, now moving to an lp8k-based board the PLL seems neither to lock nor output anything)19:01
daveshahJust to double check, are you on the latest nextpnr? Some PLL fixes were merged in a few weeks ago19:03
daveshahAlso, which package/boards are involved?19:03
daveshahI don't think there is a PLL difference for the LP8K/HX8K, but the maximum frequency achievable for a design will be lower on the lp8k19:03
daveshahCerpin: ^19:04
CerpinCurrent up to about 20 hours ago. Seems to show 99.5 MHz as my max possible and I'm running with 60. I'm using a TinyFPGA now; Lattice's HX8K breakout before19:09
CerpinErr, BX though I guess that's probably a given19:09
daveshahShould be fine19:10
CerpinI probed the clock pad on the tiny and the MEMS oscillator seemed to be at 16MHz at should19:10
daveshahWould you be OK putting your code somewhere?19:10
CerpinSure, one moment19:13
CerpinOk, the PLL instantiation is here  , and the formerly working code it's used in is here (the usbpu thing was added during testing, I didn't have that when I used it on the HX8K board)19:17
tpbTitle: show at bpaste (at
daveshahDid you change the PLL config for 16MHz input?19:18
CerpinNo, I did not. That's probably it :\19:19
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CerpinLooks like things are functional again -- this found something subtly wrong in my design that arachne didn't, thanks for your work on next!21:06
daveshahCerpin: good to know it's working!21:07
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