Saturday, 2018-11-24

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adamgreigI have an ice40 hx8k design using a pll with a clock into GBIN0 (on the same cell as the X16/Y33 PLL); arachne places fine but nextpnr errors saying the PACKAGEPIN for the SB_PLL40_PAD must be GBIN5 (X16/Y0, the cell with the other PLL)01:44
adamgreigI'm guessing it's picked the other PLL and then complained that the pad input is not in that cell, but I'm not really sure01:44
adamgreigany ideas?01:45
cr1901_modernadamgreig: You may wish to talk to tnt in ##openfpga. He's been tweaking PLL stuff lately01:46
adamgreigthanks, I'll try him01:47
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tntI'm a bit confused.  I have `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))    and   $display(" %d", `MAX(0, $clog2(1 << 17) - 18));16:52
tntand this displays -1 ... I would expect 0 (and that's what I get with iverilog)16:53
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ZipCPUtnt: That might depend upon the type of _a and _b.  Are they both signed, or not?16:58
ZipCPUIf I re-interpret -1 as an unsigned value, it will always be the maximum value16:59
tntwell, one argument is 0 exactly and the other is $clog2 which I'd expect to be signed.17:00
ZipCPU... and to how many bits is the result applied?17:00
tntit's used as the width of something.17:00
tntlocalparam XXX = MAX(0, $clog2(1 << 17) - 18);     and XXX will be -1.17:01
tntsorry, localparam integer XXX = ...17:01
ZipCPUDo you have a 5-10 line example somewhere that I could test?17:02
tpbTitle: module test; `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b)) localparam intege - (at
ZipCPUSo is your problem iverilog or yosys?17:05
tntI mean, MAX(0,-1) should return 0 ...17:06
ZipCPUNot if there's a type conflict between signed and unsigned ... but let me test this out17:06
tntAFAIU  contants like '0' or '18' should be 'integer' in verilog by default.  $clog2 is also supposed to return an integer according to the spec I have. So everything in that expression is of type 'integer' which is a signed type.17:08
ZipCPUI see what's going on17:08
ZipCPUI'm using yosys for my test17:08
ZipCPUyosys has an assertion failure reading this code ...17:09
ZipCPUVerilator has a problem with this code too17:10
tntWhat's wrong with it ?  Seemed perfectly valid to me ?17:10
ZipCPUIt may be that I modified it slightly to create a wire of width [X-1:0]17:11
ZipCPUIf 'X' is 0, the wire has zero width17:11
ZipCPULet me adjust it for a width of [X:0] ... that should help this example along17:11
sorearI thought it created a little endian wire of width 217:12
tntyeah the -1:0 thing is how I noticed th eproblem ... because yosys would throw a warning about reverse part order and truncate the signal and strip out all my logic ... and I narrowed it to that constant being miscomputed.17:12
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ZipCPUI wonder if removing the macro would change anything17:13
tntnot really17:15
tntinitial $display("%d", ($clog2(1 << 17) - 18) > 0 ? 1 : 0);17:15
ZipCPUIf not, then that eliminates one possible part of the problem.  (Testing now)17:15
tntthis displays 1 ... so -1 > 017:16
ZipCPUWhat's the type of $clog(X)?  That'd be a good question ...17:16
* ZipCPU looks up the SV spec17:16
tntThe way I understand 17.11.1 of  it should be 'integer'17:18
ZipCPUOk, so the argument is always treated as unsigned.  That doesn't tell me much of the result17:18
ZipCPUYes, integer is what I've got here too17:18
* ZipCPU greps through yosys code to find the $clog2 implementation17:19
ZipCPULooks to be in frontends/ast/ ...17:20
tntand is_signed is set to false.17:22
ZipCPUYosys creates an integer with it ...17:22
ZipCPULet's stuff a printf in there and see what integer comes back from $clog2 ...17:22
tntmkconst_int(uint32_t v, bool is_signed, int width)17:22
tntif you take the result of clog2 and put it in an integer, then use it ... it works.17:24
ZipCPUReally?  Ok ... (still digging)17:24
ZipCPUWhat result are you using for $clog2?17:27
tntWhat do you mean ?17:28
ZipCPUYou are using 17 for the result of $clog2(1<<17), right?17:31
ZipCPU(Seems obvious I know ...)17:31
ZipCPUHaving now instrumented to look at what yosys is doing internally ... I'm now more confused than I was before.17:32
ZipCPUAhh ... that's why ... it's subtracting one from the argument ... so it's working on (1<<17)-117:33
ZipCPUThat still doesn't make any sense17:34
ZipCPUCounting 1's bits would only work for values of the form (1<<x)-117:34
tpbTitle: [Diff] diff --git a/frontends/ast/ b/frontends/ast/ index bb4c97 - (at
tntthis makes it works as I'd expect.17:36
* ZipCPU searches on the definition of mkconst_int17:36
ZipCPUBut ... $clog2 *should* be an unsigned value17:42
ZipCPUIt's like ssize_t ... there's no way it can be negative17:42
ZipCPUSubtracting 18 from 17u should result in -1, but in an unsigned context ... -1 is the largest possible value17:43
tntThere is no way it can be negative, but it should still be a 'integer' signed type as far as verilog is concerned.17:44
ZipCPUYeah, okay ... I see that in the spec17:44
ZipCPUThanks for bringing that back to my attention17:44
ZipCPUCan I convince you to create a pull request with this information in it?17:45
ZipCPU... and an issue documenting that pull request?17:45
ZipCPUI'll have a chance in a couple of days to make sure it gets the attention it needs.17:45
tntIf you can comment on  and associated PR at the same time :P17:51
tpbTitle: Feature request: Finer grained control on Clock Enable usage · Issue #700 · YosysHQ/yosys · GitHub (at
ZipCPUIs that your PR as well?17:53
daveshahI understand Clifford is about to travel to the US. So there might be a little delay on this stuff right now17:54
ZipCPUdaveshah: what path forward do you recommend?  Can you accept pull requests?  This one is pretty simple17:55
daveshahNo, I don't have permission for that17:55
ZipCPUOk, we'll just hold on to these for Clifford then17:56
tnt#700 might be a bit 'unrefined' option, but at least so far I've had a good experience with it. I think pretty much all the designed I used this with ended up smaller and faster.18:09
daveshah tnt: without min_ce_use: 8 runs of picorv32 `min = 53.88 MHz, avg = 56.57125 MHz, max = 60.05 MHz`18:21
daveshahwith min_ce_use=4: 8 runs of picorv32 `icetime: min = 57.28 MHz, avg = 61.33375 MHz, max = 64.6 MHz`18:21
daveshahwith min_ce_use=8: 8 runs of picorv32 `icetime: min = 57.14 MHz, avg = 62.78874999999999 MHz, max = 67.06 MHz`18:21
daveshah11% improvement is very nice18:22
tntdaveshah: nice :)18:24
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kc5tjaZipCPU: yt by any chance?22:08
ZipCPUWhat's up?22:08
* ZipCPU is working on another tutorial lesson22:09
ZipCPUStuck on anything?22:09
kc5tjaApologies for disappearing for months; but I'm running into an issue with Verilator where it cannot find verilated.h.22:09
kc5tjaMy goal is to write an integration test for the SIA core using Verilator.22:10
ZipCPUDo you have verilated.h in your distribution?22:10
kc5tjaLet me be more precise.22:10
ZipCPUOk, so this is just a gcc issue.  Go on.22:10
kc5tjaIt's in the Verilator package.22:10
kc5tjaI'm not finding it in the obj_dir directory, though.22:10
ZipCPUOh, dear.  But yet you can run it, right?22:10
kc5tjaI can run other Verilator tests OK.22:11
ZipCPUYes, you've been doing very nicely with it from what I saw last22:11
ZipCPUGo on22:11
ZipCPUAre you using the -exe flag?  (I don't normally do so, but it might affect this)22:12
tpbTitle: Kestrel-3: Artifact Content (at
kc5tjaThat's my Makefile.  It's basically where you and I left off last time.22:12
kc5tjaThis appears to work for you, but for me, I just can't get it to locate verilated.h.  Any ideas?22:13
ZipCPUI've had this problem (I think) once or twice when using -exe.  I don't normally use -exe, so I don't have it that often.22:13
ZipCPUDoes it create an obj_dir directory?22:14
kc5tjaIt does.22:14
kc5tjaActually, let me double check.22:14
kc5tjaLike I said, been 2 months since I last did this.  ;-)22:14
ZipCPUIs there a reason why your "make -j ..." command doesn't include a number of processors?  (Let me check if this is even legal ...)22:14
kc5tjaLOL...OK, egg on my face.22:15
ZipCPUOk, -j with no argument is legal22:15
kc5tjaI typed "rm -rf obj_dir; make verilator_test" and it not only succeeded to compile, but now it ran.22:15
ZipCPUGlad I could help you!22:15
kc5tjaRubber ducking for the win, I guess.22:15
ZipCPUWow, that was one of the easier questions I've managed to help some one with.  Got any harder ones?  (Those are more fun)22:16
* ZipCPU needs rubber ducks from time to time too22:16
ZipCPUI remember a bug I was struggling with where I was *convinced* yosys was _BROKEN_!22:16
ZipCPUI had an assertion that if (A) then (B) must be true on the next clock.  I could cover(A), but never cover(B)22:17
ZipCPUThe assertion passed, cover(B) did not22:17
ZipCPUIt took some time, but I finally managed to corner clifford and get him to look at my code.22:17
ZipCPUHe found the line that essentially said: assume(!B);, and suggested that the error message needed to be more comprehensible22:18
ZipCPUSame sort of thing.  I was quite frustrated with myself for not handling my own work, but ... sometimes we all need another pair of eyes.22:18
daveshahI've had some fun bugs like that22:19
kc5tjaNow I have to make sense of the VCD output.  Heh.22:19
ZipCPUI just hate bringing others in to stare at my ... bad designs22:19
daveshahSpent two days debugging the first stage bootloader DDR3 init of an Allwinner A64 processor22:19
daveshahTurned out I'd put a 240kohm resistor instead of 240 ohm for the memory's Zq calibration resistor22:20
daveshahIt's not as bad as when my SDR project worked fine with some standalone software but failed to calibrate when part of gnuradio22:24
ZipCPUGo on22:24
daveshahBasically, both the AD9361 and something within gnuradio defined a function with the same name and a similar purpose, to do with the position of the first one bit in a word iirc22:24
daveshahBut the way the defined it differed by one22:25
ZipCPUDoh!  That one would've been a pain to find!  I'd never look there22:25
daveshahThe dynamic linker chose the gnuradio one which subtetlty broke the AD9361 init code22:25
daveshahI only found it by dumping the SPI data sent and received over USB to a file and comparing it in both cases22:25
daveshahEventually I found the specific command that was failing22:26
daveshahAnd traced this back to where it was implemented22:26
ZipCPUI would've groaned pretty hard on finding something like that22:29
ZipCPUThat would've also probably ended my work day22:34
kc5tjaThis is one of the reasons why I'm not a terribly big fan of dynamic linking as it's implemented on Windows or Posix environments.  But, I'm an old man screaming at clouds.  ;)22:35
kc5tjaOOH, I totally forgot that your code pulses the clock and nothing happens right on an edge.22:48
kc5tjaThat will take me some getting used to.22:48
ZipCPUTrust me ... it'll save you from some other bugs ... ;)22:48
ZipCPUThat said, I'd love to hear an alternative22:48
kc5tjaI'm very used to looking at the VCDs that yosys generates where things happen on edges.22:49
kc5tja(It's also how I typically did my unit tests in the past, since it was less code)22:49
ZipCPUI'd love to have things happen on edges22:49
ZipCPUI wish I could22:49
kc5tjaI'm not saying it's wrong; it's different from what I'm used to by many years.  Going to take some mental adjustment on my part.22:49
ZipCPUIt took me some adjustment as well ... after a lot of frustrating debugging with Verilator22:50
kc5tjaEverything will work great until it doesn't.  ;)22:52
ZipCPUYes.  So IMHO, the design process is all about mitigating the pain when things don't work22:53
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