Saturday, 2018-11-17

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maikmertenawesome, seems nextpnr now also takes posedge/negedge timing into account12:36
maikmertenInfo: Max frequency for clock 'uart_inst.CLK_I_$glb_clk': 26.25 MHz12:36
daveshahyes, it does now12:36
maikmertenso my fmax is *not* 50+ Mhz12:36
maikmertenand with 25.125 MHz, I'm awfully close12:37
daveshahcurrently it doesn't take into account duty cycle either12:37
daveshahif your clock's duty cycle isn't 50% that eats into your margin further12:37
daveshahthat isn't a problem for same edges paths12:37
maikmertenit *should* be 50%12:37
maikmertenbut who knows ;-)12:37
maikmertenbut at least that would perhaps explain the "some seeds work, some not" problem I encountered a week ago12:38
maikmerten(of all the components, I wouldn't have guess that the UART may be the limiting thing)12:42
daveshahis that actually on the critical path?12:43
daveshahthe name of the clock doesn't tell you what's limiting Fmax12:44
daveshahit's just to do with how Yosys resolves names12:44
maikmertenseems it's not actually the UART itself - if I comment that out another peripheral just takes its place12:47
maikmertenI guess its just a bad idea to have the CPU control logic on the negative edge12:48
daveshahnextpnr should print a critical path report telling you what is limiting Fmax12:48
daveshahhowever, abc tends to mangle net names badly12:48
tpbTitle: debian Pastezone (at
maikmertenInfo: Max delay <async>                          -> posedge uart_inst.CLK_I_$glb_clk: 6.30 ns12:51
daveshahthat one isn't so important - that's the delay to/from IO to a register12:51
daveshahthe important one is the long posedge -> negedge report12:51
daveshah*negedge -> posedge12:51
daveshahlooks like it starts around  cpu_inst.instr[3]  and ends around cpu_inst.alu_inst.sub[32]12:52
daveshahwith a big carry chain in between12:52
maikmertenooh, right12:52
maikmerten18.4 ns accumulated delay, if I read things right12:53
maikmertenI must confess I find that long one hard to read, because that all seems to be autogenerated fluff ( ;-) ) that I can't directly map to design names12:55
maikmertenah, no, I see cpu_inst.instr[3]12:56
maikmertenthat's the CPU's instruction register12:56
maikmertenand then later cpu_inst.alu_inst.sub[32]12:57
maikmertenwhich is the subtraction result in the ALU12:57
maikmertenokay, that explain a lot12:57
maikmertenthe instruction is fetched from the data bus and stored in the instruction register. From there, my asynchronous decoder will assemble the immediate value. That goes through some muxer to the second ALU input, and goes into asynchronous subtraction logic12:59
maikmertenso the asynchronous logic path is long. Really long.13:00
maikmertenactually s/asynchronous/combinatorial13:04
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