Thursday, 2018-11-08

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maikmertenI've switched to nextpnr-ice40 recently, but found that some seeds, my design would not work as intended.13:54
tpbTitle: nextpnr-ice40 seed (extension board, no cache) - Google Sheets (at
maikmertenI never *noticed* such things with arachne-pnr (which may, of course, be luck)13:55
maikmertenhow would one tackle such issues where simulation is fine, most synthesis runs are fine, but for *some* seeds things just don't work out?13:56
daveshahthe best approach is to do a post-pnr simulation using icebox_vlog to go back to a netlist13:57
daveshahhowever, this won't simulate timing issues13:57
daveshahdo you have any inverted clocks in your design?13:57
maikmertenI have only one clock, but the control logic acts on the falling edge, while stuff like the ALU, bus unit etc. act on the rising edge13:58
daveshahI would say these can cause weird timing issues because at the moment (this will be fixed soon in nextpnr's own timing analysis) they aren't taken into account. But the fact your design's Fmax is double your operating clock more or less, then this wouldn't be the problem13:59
maikmertenah, okay14:00
daveshahdo you rely on initialised bram?14:01
maikmertenyes (boot ROM), which is why I keep the system in reset for 2048 cycles14:02
maikmertenthere's a strange bram errata IIRC14:03
daveshahbut 2048 cycles is more than enough to mitigate it14:03
maikmertenyeah, but I also need to make sure the cache tags are invaldidated on reset ;-)14:04
maikmertenand my horrible solution to that is to write zero to the cache tags one entry after another on each clock when reset is asserted ;-)14:04
maikmertenso... just in case this happens due to my usage of inverted clocks and thus skewing timing results... arachne-pnr wouldn't care for that because all it does it to keep signal paths short, no matter what the clock?14:07
daveshahthe timing weighting in nextpnr isn't that big tbh14:07
daveshahI don't think this is an inverted clock issue14:07
daveshahassuming your duty cycle is near enough 50%, your design passes timing even considering the inverted clocks14:08
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daveshah*clock duty cycle14:08
maikmerten\o/ net split, woooo!14:08
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maikmertenokay, thanks :-)14:09
maikmertenguess I'll do similar tests with arachne-pnr. Perhaps I just was lucky all the time and I'll find out that some seeds for arachne-pnr fail as well14:10
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maikmertentested again with arachne-pnr:
tpbTitle: nextpnr-ice40 seed (extension board, no cache) - Google Sheets (at
maikmertenthe good news is that I don't need to switch back to arachne-pnr15:26
maikmertenthe bad news is that not hitting any problems earlier with arachne-pnr was most likely just luck15:26
maikmertenthere must be some critical timing stuff going on in my design15:27
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daveshahit could be metastability?15:28
daveshahif you have different clock domains or external IO15:28
maikmertenonly one clock driving everything15:29
maikmertenheh, perhaps a silicon defect in my iCE40 ;-)15:29
maikmertenthese tests were conducted with external SRAM attached to the FPGA board, this would of course add considerable room for timing issues15:31
maikmertenbut I distinctly remember issues appearing with BRAM-only as well15:31
daveshahI dare say it, but it might be worth seeing what happens in the vendor tools15:40
daveshahThey do perhaps have better timing, and rule out any possible icestorm bugs15:40
maikmertenyeah, I might have to resort to that. I hear icecube2 is full of excellence.15:48
maikmertenwow, Lattice presents me a registration page via HTTP. Manually changing to HTTPS works... at least.15:52
cr1901_modern"icecube2" and "full of excellence" in the same sentence. I must've jumped between timelines recently...15:54
maikmertentimelines all right
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maikmertenoh my, icecube2 is 32 bit. Great.16:13
maikmertenawwwww, maaaaan. It wants a license file. They happily send me a license file tied to my NIC. And then it complains that license file does not match my NIC. Excellent!16:32
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bluesceadamaikmerten, if you are in linux it might be due to icecube2 relies on using "eth0", newer distros don't use that naming scheme anymore17:39
bluesceadaeasy solution is to load the dummy module17:40
bluesceadathen do ip link add dev eth0 type dummy17:40
bluesceadaand give it any mac address you want with ip link set dev eth0 address 00:11:22:33:44:5517:40
maikmertenoh my. That's excellence right there.17:42
bluesceadaif you heard it with tuntap devices before, I prefer a dummy interface over that. At least on notebooks where you might use network-manager for all sorts of connections, a tuntap device sometimes can confuse it17:42
maikmertenthanks for the hints17:43
bluesceadait is anyway ridiculous "security", even on a 'real' eth0 device you can 1. rename it in software 2. often change the mac in software anyway ...17:44
maikmertenI guess that's manager-type security17:46
maikmertenbluesceada, cool, thanks, that worked wonderfully17:51
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maikmertenokay, I guess I see now why iCECube2 is not universally referred to as being excellent.17:59
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mithroHas anyone played with RAM4K initialization options on the ice40 before?18:37
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