Wednesday, 2018-10-31

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maikmertencan BRAM-inference for iCE40 also work when reading with a blocking assignment? I'm trying to define a cache that determines a cache hit/miss within one clock cycle, so I need the tag information available in that clock tick. I guess that's not something BRAM can provide?14:32
maikmertenhttps://paste.debian.net/1049849/14:32
tpbTitle: debian Pastezone (at paste.debian.net)14:32
daveshahmaikmerten: no, that won't work on ice4014:44
daveshahyou'd have to find an fpga with distributed ram14:44
maikmertenthanks :-)14:44
maikmertenI guess having a cache-lookup cycle it'll be then ;-)14:45
sorearalso, distributed ram tends to be much lower capacity than block ram on chips with both14:48
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daveshahsorear: not always a downside in some cases like register files, where a whole bram would be  a waste anyway14:59
sorearindeed15:00
sorearbut a cache memory is more likely to be sized to use the ~entire chip15:00
sorearespecially on non-UP ice40 where you only have 16KB total15:00
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maikmertenfor getting my feet wet with caches, I'm going for a cache with 256 entries, each 32 bit wide (which fits nicely into 2 iCE40 BRAMs) and 256 16 bit tags (1 bit valid, 15 bit address)15:19
maikmertenand then work my way up ;-)15:19
maikmertenwill only accept aligned 32-bit words... essentially geared towards being an instruction cache15:20
soreardirect-mapped cache covering 32 MB of address space?15:21
maikmertenyeah, it's going to be a horrible cache-trash fest15:23
maikmertendirect-mapped, write-through, massive 256 words in capacity... what's not to like? ;-)15:24
sorearwhat sort of external memory15:25
maikmerten8-bit wide external SRAM15:25
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maikmertenso currently my CPU needs in total about 6 cycles to fetch the next instruction15:26
maikmertenthis is basically the RISC-V equivalent to an Intel 8088 ;-)15:27
maikmerten(but that one at least had a prefetch queue)15:27
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sorearwhat can the external sram do latency/throughput?15:28
maikmertenI'm currently using the SRAM with one cycle latency (present address at one clock edge, get the data one cycle later)15:31
maikmertenthe chip itself can do 10ns cycle times15:32
maikmertenbut due to the board layout and connectors and because I'm sampling data mid-cycle, I can only drive it at ~30 MHz15:32
sorearasync SRAM?15:33
maikmertenfor now I've settled for 25.125 MHz, which happens to be very close to [email protected] VGA timings15:33
maikmertenyes15:33
maikmerten512Kx815:33
soreari guess you could do 4-bit color and dedicate 50% of the memory cycles to scan-out15:34
maikmertenon this extension board for the iCE40 HX8K eval board: https://github.com/maikmerten/hx8k-breakout-extension15:34
tpbTitle: GitHub - maikmerten/hx8k-breakout-extension: A PCB with SRAM, buttons, LEDs and some pmod-compatible connectors for the Lattice HX8K Breakout Board (at github.com)15:35
maikmertenyes, with some cleverness I guess one could drive VGA from that SRAM as well.15:36
sorearoh I though you were saying you were already going to do VGA15:39
sorearalthough real-time chargen/sprites is also an option15:39
maikmertenwell, in the future I might want to do VGA. Back when I did something similiar in VHDL (pre-yosys), I already had a simple RISC-V SoC with VGA15:59
maikmertenthat one generated 40x25 characters15:59
maikmertenwith a chargen for 256 8x8 pixel chars16:00
maikmertenwhich is rather compact and can be done in BRAM16:00
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maikmertenokay, a first implementation of my "aligned word only", "only word reads get into cache", direct-mapped, 256 entry cache works now19:01
maikmertendhrystones go from 4105 per second to 4655 per second, a 13.3% performance increase19:02
maikmertenressource util goes from 1857 LCs (no cache) to 1938 LCs (with cache), BRAMs from 5 to 8 (of 32)19:06
maikmerten(so a 4.3% increase of LC usage for 13.3% better performance... that's ok I guess)19:07
soreardoes it cache instructions, data, or both19:08
maikmertenevery aligned word read gets offered to the cache19:09
maikmertenso no proper separation19:09
maikmertenalso, every write invalidates the respective cache line19:10
maikmertenso the cache is a) small and b) gets invalidated a lot19:10
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