Thursday, 2018-07-26

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mithroZipCPU: Do you know what "ERROR: Failed to import cell $techmap\gold.$procdff$3319 (type $adff) to SAT database." mean - do I need to do something like adff to dff or import ?01:42
tpbTitle: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at
ZipCPUHi, mithro01:43
ZipCPUI hate to ask, but .... what are you trying to accomplish?  I normally only get the adff bug when doing formal methods01:43
ZipCPURegular synthesis?01:44
mithroTrying to prove equivalence of a bitstream to initial verilog using a magic script that daveshah gave me :-P01:44
ZipCPUAre you using symbiyosys, or just yosys?01:45
ZipCPUyosys-smtbmc that is01:45
ZipCPUwell ... I guess I mean yosys/yosys-smtbmc .... 'cause the answer is different depending on which you are using.01:45
mithrosymbiflow-arch-defs/env/conda/bin/yosys -p "rename top gate; read_verilog symbiflow-arch-defs/ice40/tests/ffpack/example.v; rename top gold; hierarchy; proc; miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter; sat -dump_vcd symbiflow-arch-defs/ice40/tests/ffpack//build-ice40-top-routing-virt-hx1k/out.vcd -verify-no-timeout -timeout 20 -seq 1000 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs01:46
mithromiter" symbiflow-arch-defs/env/conda/share/yosys/ice40/cells_sim.v symbiflow-arch-defs/ice40/tests/ffpack//build-ice40-top-routing-virt-hx1k/example_bit.v01:46
ZipCPUOk: add clk2fflogic to your flow.01:46
mithroZipCPU: after the proc?01:47
mithroZipCPU: What does the clk2fflogic do?01:48
ZipCPUThe problem is ... without the clk2fflogic, yosys may or may not handle the asynchronous reset's properly.01:48
ZipCPUclk2fflogic separates the clock within the design from the SMT timestep.  The clock becomes a separate input that may need to be assumed to be toggling.01:49
mithroOkay, this definitely has an async reset01:49
ZipCPUIt helps with async resets.01:49
ZipCPUThat said, Clifford recently fixed SymbiYosys up for me so it didn't need clk2fflogic in order to implement async resets.01:49
ZipCPUNot really sure what he did different.  (That was this week or last.)01:50
tpbTitle: Snippet | IRCCloud (at
ZipCPUIf you just run symbiyosys, you might see a different (perhaps better) yosys/command/approach ...01:50
* ZipCPU pulls up a browser ...01:50
mithroI should expand `-timeout` I assume?01:52
ZipCPUNot sure.01:53
ZipCPUI've actually never used the equivalence checking myself.01:53
mithroIs it likely something with 1233925 variables and 3262769 clauses likely to finish?01:53
ZipCPUI've never seen that statement before.  I don't know.01:54
mithroWell - it does seem to have finished....01:55
mithroIf I recall correctly, any time the cmp_ values is not 1 is a case where the circuits differ...01:56
mithroI actually think I can do something simpler - just run both verilog files with the same test bench and then compare the output....01:59
mithroThink that shows the two circuits aren't logic equiv but not really sure...02:06
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ZipCPUAnother interesting test: Create a top level feeding both circuits the same inputs, and asserting that the outputs are the same.02:20
ZipCPUIt's not quite as good as equivalence checking, but ... it's more along the lines of the parts of yosys I've personally used.02:20
ZipCPUOnly problem is .... if you can't get an assertion failure in the first N clocks, the conclusion you are looking for will be undetermined.02:20
mithroZipCPU: This is the bug we have been thinking about ->
tpbTitle: Create an ice40 test for the packing of different types of flip flops together · Issue #144 · SymbiFlow/symbiflow-arch-defs · GitHub (at
* ZipCPU takes a peek02:23
ZipCPUHow many LUT's are in your comparison?  1?  8?  Many more?02:25
mithroZipCPU: Hrm? In this test we don't really care about the LUTs here... Just having enough flip flops to test packing is working...02:30
ZipCPUAhh, sorry ... wrong term ... thanks for the correction.02:30
mithroZipCPU: The packer uses connectivity to pack together -- so, interested in different groupings and making sure that the packing is doing the right thing02:38
mithroSome FF types can be packed together into a tile, some can't, etc02:39
mithroZipCPU: But too lazy to write all the tests by hand :-P02:42
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mithroSo it seems that yosys can't import it's own simlib.v? ERROR: System task `$stop' outside initial block is unsupported at symbiflow-arch-defs/env/conda/share/yosys/simlib.v:1282.02:58
mithroSeems like I need something like -DSIMLIB_NOCHECKS ?02:58
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mithroZipCPU: Have you used yosys's "sim" command?03:34
ZipCPUNo, I haven't.  I love what I can do with Verilator way too much.03:41
mithroZipCPU: Any chance you'd be interested in adding a verilator version of these commands -> and ?03:49
tpbTitle: symbiflow-arch-defs/ at ffpack_tb_sr · mithro/symbiflow-arch-defs · GitHub (at
ZipCPULet me take a peek in the morning, it's getting quite late here.03:50
mithroZipCPU: No hurry, the iverilog version works okay03:54
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ZipCPUmithro: Looking at the iverilog Makefile commands you cited last night.  I'm curious ... how long does iverilog take to do these simulations for you?12:21
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maikmertenmattvenn, some more work on the HX8K breakout board SRAM/PMOD wing - now with buttons ;-)15:29
tpbTitle: Pasteboard Uploaded Image (at
mattvennlooks good!15:32
mattvennI take it there aren't enough pins to get a 8pin pmod on the bottom?15:32
mattvennalso - liking the silkscreen on the pmods - nice work!15:32
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maikmertenmattvenn, sorry, not enough pins available for another 8-pin :-(15:33
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maikmertenhmm... having the decoupling capacitor for the SRAM that far away somewhat defeats the purpose15:35
* maikmerten tries to remedy this15:35
mattvennnot a big deal15:36
mattvennI can't see the back, but assuming you're using another 8 wires for the sram on the back15:36
mattvennif you don't have 8, then use them all up with buttons and leds!15:37
mattvennsorry I meant 415:37
mattvennas you've already got 415:37
mattvennkeep me posted. I've got to go early today - will check back tomorrow15:38
maikmertenyeah, I'm routing some SRAM signals on the back side - which is why there's a row of vias on the south-east of the SRAM chip15:40
maikmerten(the resistor network for those is also on the back)15:41
maikmertensomewhat better decoupling:
tpbTitle: Pasteboard Uploaded Image (at
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mithroZipCPU: A couple of seconds at the moment16:59
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ZipCPUmithro: Then it doesn't sound like you need a redesign at all, right?18:38
mithroZipCPU: Nope - don't need a redesign -- just want to add support for verilator as an alternative to iverilog -- probably be useful for faster simulation when we have bigger designs....18:38
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mithroZipCPU: IE Full SoCs18:48
ZipCPUHeheh ... Full "post-synthesis" SoC's?  That'd be ... a fun challenge.  I know I use Verilator on full SoC's often enough myself, just never post synthesis.18:49
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mithroZipCPU: sorry, post pnr - not post synthesis22:00
ZipCPUFrom a Verilator standpoint, there wouldn't be any difference.22:01
ZipCPUIn both examples, you lose one of the great benefits of Verilator--being able to do word ops.  The other great benefit of Verilator is being able to operate on 0 and 1, rather than 0, 1, z, and x.22:02
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