Tuesday, 2018-07-24

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mattvennI'm having a problem with a fairly simple design15:31
mattvennI'm testing Kevin Hubbard's hyperram double pmod board with his module hyper_xface.v15:32
mattvennI've wired this up and it looks like it's working OK15:32
mattvennI've put a serial interface in15:32
mattvennso I can write addresses and read and write data15:33
mattvennand am getting strange problems with bytes crossing serial boundaries on the way out15:33
mattvennso an internal counter might get to 32, and this results in 8192 on the serial receive15:33
mattvennremoving the hyperram module removes this problem15:34
mattvennso it looks to me like a timing issue15:34
mattvennunfortunately, icetime fails with Unable to resolve delay for path ce -> ltout in cell type LogicCell40!15:34
mattvennand google isn't helping too much on that15:34
mattvennyou can take a look at top.v here: https://github.com/mattvenn/hyperram/tree/icestick-example15:35
tpbTitle: GitHub - mattvenn/hyperram at icestick-example (at github.com)15:35
mattvennany guidance appreciated!15:36
daveshahmattvenn: the ce -> ltout is hopefully fixed in the latest icestorm (by funny coincidence this issue that has not surfaced for years was found a few weeks ago by someone else)15:36
daveshahhowever I wouldn't expect to see that at all in a design from arachne-pnr?15:37
mattvennis it to do with with SB_IO blocks I'm using to get inout pins working?15:38
mattvennyes, new icetime works with no errors - timing estimate of 105MHz, so my guess about timing isn't correct15:40
mattvennmy target is the icestick, with a 12Mhz clock15:40
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mattvennsome other strangeness. If I assign a new pin to the serial tx so I can look at it on the scope16:09
mattvennoutput tx216:09
mattvennassign tx2 = tx;16:09
mattvennthen the serial port stops functioning, no bytes ever sent16:09
mattvenn(with hyperram module enabled)16:10
mattvennwith hyperram removed - all works as expected16:10
mattvennI don't really know how to progress from here16:10
mattvennwhy would adding a new wire stop the design from working?16:11
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maikmertenyay, first take on a very ugly SRAM and PMOD "wing" for the HX8K breakout board... https://pasteboard.co/HvYoBXzG.png18:13
tpbTitle: Pasteboard Uploaded Image (at pasteboard.co)18:13
ZipCPUmattvenn: Are you using any PLL's in your design?18:27
elmsice40 question, how can I configure a logic cell to use a DFF to use the CEN, but another cell in the same tile use a DFF with enable set to 1?18:38
elmsIt's not clear from http://www.clifford.at/icestorm/logic_tile.html but it looks like it should be possible in figure 2.2 of iCE40 LX/HX family datasheet18:40
tpbTitle: Project IceStorm LOGIC Tile Documentation (at www.clifford.at)18:40
daveshahelms: no18:40
daveshahCEN of 1 is simply disconnecting the CEN to the whole tile18:40
elmsyou mean it's not possible?18:40
daveshahNo, its not possible18:40
elmsare the enable and output mux ganged? https://usercontent.irccloud-cdn.com/file/cVzKFFrp/iCE40-PLB.png18:42
daveshahYes - I can't see any reason why you would use them separately anyway18:42
elmsyeah, trying something with VPR and it's packing some together such that one has a cen and one is always 1. Guess we need to stop those from being packed in the same time. Thanks!18:44
daveshahYes, you will need to18:45
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mattvennZipCPU: no plls18:48
ZipCPUOk, then that's not your problem.18:48
mattvennthe only other time I've experienced things working funny on addition or removal of a wire or register was due to timing issues18:49
mattvennmaikmerten: looks cool! are there spare wires you can use for more pmods?18:50
ZipCPUmattvenn: I'm also struggling to understand what would cause your issue(s).  It's not making sense here, no matter how many times I read your description.18:51
ZipCPUmattvenn: To understand why icetime is failing, let me ask how many clocks are being used in your design?  (I know you said you weren't using any PLL's)18:59
maikmertenmattvenn, some pins are left, but not enought for a 2x6 PMOD18:59
maikmertenthose 2x20 headers carry surprisingly few signals19:00
maikmertengiven that there's about 10 GNDs per connector19:00
maikmerten*there are19:00
maikmertenalso it's a hazzle to route signals between those pin headers to the right hand side, which explains the weird lines at the top of the board19:02
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tpbTitle: Pasteboard Uploaded Image (at pasteboard.co)19:06
maikmerten(a pin header with 1x6 pmod signals should be doable)19:08
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* maikmerten adds a 1x6 PMOD header to the design19:14
mattvennlet me know when you put in on oshpark19:20
mattvennZipCPU: daveshah told me the bug had been fixed and I verified timing is OK with a new icetime19:20
mattvennonly one clock19:21
mattvennwell.. the uart generates a baud clock19:21
mattvennso I guess that's another19:21
maikmertenmattvenn, https://pasteboard.co/HvYQQru.png19:22
tpbTitle: Pasteboard Uploaded Image (at pasteboard.co)19:22
maikmertenmattvenn, sure, I'll happily share the design19:23
mattvennone problem I discovered using sram on the blackice board was that they'd used a global PLL pin in the i/o19:23
mattvennwhich meant only 1 PLL could be used if the sram was being used19:24
mattvennso might be worth checking the pins that would need to be inout for the sram aren't the PLL pins19:24
maikmertenone the hx8k breakout board the clock is on J319:25
* maikmerten checks this is not used on the SRAM19:25
maikmertenewww, J3 is on header "J4", and yes, I'm currently happily using that for the SRAM19:27
maikmertenthanks for the hint19:27
maikmerten(why why why did they do that?!)19:27
tpbTitle: Placement conflict between SB_IO (for RAM) and PLL? - myStorm (at forum.mystorm.uk)19:33
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maikmertenyup, oscilloscope confirms a neat 12 MHz clock on for signal "J3" on header J419:35
maikmertenyup, oscilloscope confirms a neat 12 MHz clock on signal "J3" on header J419:35
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maikmertenokay, thankfully it was easy to avoid the J3 pin without a ripple effect on the signal routing19:41
maikmertenbut my, without having this conversation I would for sure have ended up with a non-functional board19:42
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