Thursday, 2018-07-19

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promachany particular reason why multiclock induction does not follow my assume() ?02:42
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ZipCPUpromach: Go check your code again.  Either the assumption is not being hit, or it isn't assuming what you think it is assuming.03:12
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promachZipCPU: no, both situations you mentioned just now are not what causing the problem :|03:16
ZipCPUIs this a clocked assumption?03:17
promachZipCPU: again, I am not trying to blame the tool03:19
ZipCPUDoes it need to be?  i.e. does it depend upon $past?03:19
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promachyes, it needs $past()03:20
ZipCPUThe assertion that is failing, is it also a clocked assertion?03:20
ZipCPUUsing the same clock?03:21
promachassume() is in @(posedge tx_clk) , assert() is in @($global_clock)03:21
promachI have to do this way03:21
promachI cannot use the same clock03:21
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tpbTitle: UART/test_UART.v at development · promach/UART · GitHub (at
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ZipCPUHow many tx_clk's are in your induction window?03:22
promachwhat do you mean by window ?03:22
ZipCPUThe number of timesteps or depth of the proof03:23
ZipCPUAre you assuming an input to your core?  Or logic within your core?03:24
promachZipCPU: see
tpbTitle: UART/test_UART.v at development · promach/UART · GitHub (at
promachinput to the UART core03:25
ZipCPUHmmm ... not very realistic is it?03:25
ZipCPU"assuming" that the external interface will hold the data constant until the UART has finished sending it.03:26
promachwhat is wrong with that ?03:27
promachI got what you mean now03:27
promachbut that does not tell why the multiclock induction does not follow the assume()03:28
ZipCPUThe assume isn't evaluated until the tx_clk timestep.  If before that time the $global_clock assertions are evaluated, then you have a bit of a conflict.03:28
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promachyou mean race condition between always block ?03:29
ZipCPUOne solution would be to use some registers to get rid of the $past operators and make it an always @(*) assumption.03:29
promachif(enable) reg_i_data <= i_data;03:30
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ZipCPUalways @(posedge i_clk) past_i_data <= i_data;03:32
ZipCPUYou've got the basic idea, we're just arguing over variable names at this point .... and the enable line.03:32
promachjust store the data into a register when the single-pulse enable signal is asserted03:36
promachI got what you mean.03:36
promachI start to admire the beauty of always_ff03:37
ZipCPUYes, but the normal $past isn't driven with an enable, but rather with a clock transition.03:37
promachI am not going to use $past for assume03:37
promachyou messed up the assert and assume in this case03:38
promachmy assert() does not use $past()03:38
ZipCPUI did?03:38
promachonly assume() uses $past()03:38
promachsee line 71103:38
mithroI'm obviously missing something - as it shouldn't be this hard to write a yosys pass that does what I want :-(03:39
ZipCPUYes, but reading the history on IRC ... I was referencing an assume ...03:39
ZipCPUmithro: Don't look at me!  I've never tried writing any.  ;)03:39
mithroZipCPU: There is a big piece of missing documentation around things like SigPool, SigChunk, SigBit, replace/remove, how Wires and ports are related....03:48
mithroAnd Clifford can't tell me I didn't look at the documentation, as I've got it open right here now03:49
ZipCPUmithro: I'd love to help, but I'm much more of a user than a developer of yosys at this point.03:49
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daveshahmithro: certainly I've found as soon as I find a pass that's vaguely what I want it is easy to work out what is going on06:11
mithrodaveshah: I sent Clifford a bunch of info were I got stuck and what I found confusing06:12
daveshahIMO chapter 6 of the manual looks good, although I'm not such a manual reader personally06:13
mithroI was looking at splitnets and deminout06:14
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Kokjorqou: Hey! What kind of board are using for projectchibi? I would like to help build the tools and experiment with the MAX V CPLD's.09:01
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rqouKokjo: unfortunately I currently don't actually have a board!09:04
rqoueverything that has been done has been done with only software09:05
rqouhowever, i have designed a custom board that's currently somewhere in the mail, so i expect to be able to do hardware testing soon09:05
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elmsI'm hoping someone can enlighten me about some special cases in icetime. I'm getting some errors with a picosoc using symbiflow "Unable to resolve delay for path ce -> ltout in cell type LogicCell40!" Also see that I can get "sr -> ltout"16:42
tpbTitle: icestorm/ at master · cliffordwolf/icestorm · GitHub (at
elmsdaveshah: ^^ are you familiar with icetime?16:43
daveshahelms: it might be a bug in the LutCascade stuff, given arachne-pnr didn't use it it might not be that well tested16:44
daveshahneither ce -> ltout nor sr -> ltout exist as paths, because ltout is a combinational output of the LUT only16:44
daveshahcan you share a test case please?16:44
elmsright now it involves checking out try-picosoc2 branch of vtr and symbiflow-arch-defs. I can share the asc file if that would be helpful16:46
daveshahPlease just send an asc file16:47
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daveshahelms: fixed in Thanks for the test case and report!16:56
tpbTitle: Sign in to GitHub · GitHub (at
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elmsdaveshah: thanks for the fast response. Should it also bypass for lcout like the previous
tpbTitle: icetime: Remove non-existent paths from ce/sr to ltout by daveshah1 · Pull Request #175 · cliffordwolf/icestorm · GitHub (at
daveshahelms: no16:59
daveshahlcout is the output after the flipflop (in fact the LUT/ff selection mux)16:59
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daveshahin that case, the only input that doesn't drive lcout is the carry input which only drives the dedicated carry chain carry output17:00
elmsok. Thanks again. Well that helps with icetime. Now to figure out what else is wrong as taking it back to verilog the simulation looks all wrong.17:03
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mithroIs there a way to loop over everything in a selection?20:49
mithroSeems like my best option is to go to tcl?20:50
mithro(Or C++)20:50
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mithrodaveshah: Have you seen any examples of tcl in yosys?20:59
daveshahmithro: other than trying it once back while considering options for the VPR XML stuff, not really21:03
mithroI think I'm slowly figuring it out21:04
daveshahNot much of a Tcl fan myself, but it was handy in Project Trellis21:09
daveshahOn the Lattice side21:09
daveshahUnfortunately their Tcl console had terrible memory leak issues21:10
mithroHrm -- add -input "${p}_I" 1 seems to be creating a new input with the name "${p}"21:11
daveshahmithro: what happens without the quotes?21:13
mithroHrm - it appears its not working the way I thought it was21:20
mithrodaveshah: How do I get something from a select into tcl?21:20
daveshahmithro: tbh my angle of attack with vendor tcl tools has been to do all substitution and parsing in Python scripts that read and write the output :P21:22
daveshahIt's probably a case of printing the selection and putting it into a Tcl list21:22
mithroI just want a loop :-P21:22
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daveshahmithro: so I think the first step is a select -list21:23
mithroset inout [select -list i:* o:* %i]21:24
mithroThat just writes the list to stdout21:24
daveshahThe Yosys bit of that looks good21:24
daveshahBut maybe you have to use -write and write to a temp file then read that in21:25
daveshahI tried to get this working with Lattice's tcl stuff and failed21:28
mithroOh well, guess I go back to C++21:28
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mithrow no Python? :-P21:30
daveshahThere will be Python bindings for the RTLIL side of things done over the summer, IIRC21:32
mithrodaveshah: Is there a way to just run yosys commands from C++?21:33
daveshahmithro: yes, that's exactly what the synth_$platform commands do21:34
mithroOkay, will go have a look at them21:34
mithrogoing to get coffee bblr21:34
tpbTitle: yosys/ at master · YosysHQ/yosys · GitHub (at
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