Friday, 2018-07-13

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daveshahmithro: yeah, they are much better05:52
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keesjmy presentation was .. alright. I hope I did not tell to many fairy tales. I can not look into more details into those LUT4 thingies and ice04008:25
keesj(also I have a few tinyFPGA boards comming my way, next to the icestick and .. the beaglebone capes)08:26
keesjI need to chose to either port my can controller to verilog/ice40 e.g. or do home automation (emulating 433.92 Mhz remote and controlling my beamer using IR)08:28
tpbTitle: Can HDL documentation Can HDL documentation (at
keesjbut if I understand correctly the ghdlsynth-beta might allow me to compile vhdl code on ice040
tpbTitle: GitHub - tgingold/ghdlsynth-beta: VHDL synthesis (based on ghdl) (at
keesjIs anybody interested in VHDL in here?08:30
daveshahkeesj: ghdlsynth is very experimental08:31
daveshahNo, I think most people here are Verilog people08:31
keesjThanks. I will try to focus more on the second project. it is probably a little to simple to learn about verilog but will be cool for better understanding yosys08:40
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KokjoWould it be possible to implement a fpga inside another fpga. I do understand the it would not be efficient, but how would i do it and can it be done? what it the simplest way to do this?09:15
daveshahKokjo: sure09:16
daveshahI think there are even some projects like that09:16
daveshahcan't remember any names, but I know I've seen them before09:18
Kokjodaveshah: can you point me in the right direction, googling "fpga in fpga" leads nowhere...09:18
daveshahKokjo: this is for coarsegrained interconnect09:20
tpbTitle: InterSynth - Example-Driven Interconnect Synthesis (at
keesjit it possibly also possible to run a simluator on a soft core09:20
Kokjodaveshah: you are the one reverseing the ECP5 fpga, right?09:20
daveshahKokjo: s/reversing/documenting09:20
daveshahbe careful09:20
daveshahEdmund will tell us off otherwise09:21
Kokjoim not sure i understand the difference...09:21
daveshahone word has negative/illegal connotations, the other one doesn't09:21
cr1901_modernSomeone must've gotten a stern warning for this in practice. E.g. the terms "reversing/HX4K" used to be casually discussed.09:24
cr1901_modern(on Twitter anyway)09:24
Kokjodaveshah: oh, i see. I did not know that, maybe i have been playing too much ctf, reverse engineering to has a very neutral connotations to me. reverse engineering to me is just the process of obtaining enough knowlegde about the internals of something to make it do funny things.09:24
daveshahI don't think we were told off by anyone in the FPGA companies.09:25
daveshahIt's more a general approach of attempting to work more with them more I suppose09:26
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cr1901_modernWhat does "always @(negedge 1'hx) begin" mean in verilog (yosys generates it sometimes while I experiment)?11:27
daveshahcr1901_modern: do you have a nice example where it is generated?11:30
daveshahit seems like it would come from a flip-flop without a clock11:30
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cr1901_modernRun yosys on this file: >>11:37
cr1901_modernwith this script: (up until/not including extra)11:37
cr1901_modernI.e. yosys -qp 'script bram-man.ys :extra' -l bram_man.yrp11:38
cr1901_modernThe output file bram-man-noinf will have it11:38
cr1901_modernI'm trying to force yosys to use LUTs for RAM to experiment w/ something11:41
daveshahcr1901_modern: what Yosys version are you on? not seeing it locally11:44
cr1901_modernActually I lied, that was the wrong script11:44
cr1901_modern Try this one11:45
daveshahthanks, looking into it now11:47
daveshahcr1901_modern: looking at the RTLIL it seems that the memory still uses read and write port cells internally, which Yosys doesn't dump to Verilog very nicely11:53
daveshahI don't think write_verilog is really supported without a `memory` pass first11:54
cr1901_modernThere is a "memory" pass (minus "memory_dff"). I just did it manually.11:55
cr1901_modernBut whatever, this is par for the course any time I need to black box test yosys. I modify one thing, and yosys generates stuff I don't expect11:55
cr1901_modernmeaning I'll have to spend time reading thousands of lines of C++ just to understand what's going on, decide it's not worth it, and it forever remains a mystery11:56
daveshahI think it is memory_dff that you need, that merges the write flipflop into the write port11:56
cr1901_modernBut that's what I deliberately removed to see if yosys would fallback to LUT RAM!11:57
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cr1901_modernI didn't expect that removing the memory_dff pass would make it so yosys couldn't properly utilize LUTs11:57
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cr1901_modern I like how when I run memory_collect on this toy design, $mem cells are _not_ generated12:04
tpbTitle: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at
daveshahcr1901_modern: memory_dff and memory_collect works for me12:09
daveshahafail memory_dff is pretty much required12:10
cr1901_modernmemory_collect doesn't generate a $mem cell for me even when memory_dff is enabled12:21
cr1901_modernand even though the code path to generate a $mem cell is travered12:21
cr1901_modernbleh, I'm going back to bed12:22
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tinyfpgacr1901_modern: ICE40 cannot use LUTs as RAM, only ROM15:16
daveshahtinyfpga: hi! just got the 85k board from Edmund, thanks15:26
daveshahGood encouragement to fix the current performance issue in my Trellis to PnR database importer15:27
tinyfpgadaveshah: ill upload the kicad layout today so you can find the JTAG, SPI ports and know how the pins are mapped16:27
daveshahtinyfpga: Awesome, that would be great16:28
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mithrodaveshah: I was going to complain to you about that :-P18:32
mithrodaveshah: (The speed of the Treills database importer :-)18:33
daveshahmithro: i will port it to c++ from that crappy snek thing18:33
daveshahthat fixed the routing graph builder, should fix the database deduplicator too18:33
mithrodaveshah: Actually, I think it was the compiling side of things that was taking a long time? I didn't have a lot of time to investigate before I had to run and catch a train18:34
daveshahmithro: that shouldn't be more than 20-30 secs max and could easily be fixed. It takes 6-8 minutes to build the data first18:35
daveshahwhich is also the snek bit18:35
daveshahmithro: fyi and
tpbTitle: ecp5: Adding Verilog sim models by daveshah1 · Pull Request #186 · SymbiFlow/symbiflow-arch-defs · GitHub (at
mithroDunno, it's not like I can complain - the ice40 rr_graph generator is *super slow* because of all the debugging prints and stuff18:36
daveshahmithro: to be fair, even 10 minutes is nothing compared to downloading and installing Vivado or Diamond particularly if you have the internet connection of a mere mortal18:37
daveshahnot that we can't be better18:38
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daveshahI might even get to solving those problems this weekend, now I have more motivation to do so18:38
mithrodaveshah: Even if you have Google's connectivity - downloading Vivado takes more then 10+ minutes18:38
daveshahmithro: from memory when I was downloading it on uni's ridicuously fat pipe over the summer holidays I was definitely being limited to 1-2MB/s by Xilinx's side anyway18:39
mithroIIRC digshadow managed to download and get blinky working on an ice40 device (having never used icestorm before) while waiting for Vivado to download...18:40
digshadowha yeah18:40
daveshahI'm not surprised. On a slow day you could probably get an end to end flow working from scratch in that time period18:42
* TD-Linux is slightly miffed that the ice40 doesn't have any 5v tolerant ios18:44
cr1901_moderntinyfpga: Just in case; I don't mean distributed RAM in this case18:47
mithroTD-Linux: What uses 5V's these days? :-P18:48
daveshahmy guess is it's something not from these days18:50
mithrodaveshah: Really interesting to see your work to add the ECP5 to Yosys18:51
daveshahmithro: There is one annoyance that still needs work18:51
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daveshahThe ECP5 has a FF style that is very unusual, and not following the usual silicon style. Basically synchronous set/reset has priority over clock enable - so clock enable isn't really a clock enable but just a data enable. Yosys can't extract these as it stands, so that will be a small custom pass18:52
mithrodaveshah: Interesting, I was looking at that recently myself18:53
daveshahmithro: After discussion with Clifford we agreed just to use TRELLIS_FF for now and leave the Lattice primitives for another time18:53
mithrodaveshah: That actually sounds exactly how I would suggest you do it18:53
daveshahLattice have a lot of FF primitives that are quite annoying to deal with, like FFs with a mux in front because one of their ancient architectures looked like that18:54
daveshahFor RAM I may do the same, or support both. The Lattice primitives take a C-style hex number in a string rather than a Verilog numeric parameter for initialisation18:54
daveshahYou'll see the conversion function I had to write in the DPR16X4C sim model (I wanted a Lattice-compatible DPRAM as an option, because some people manually instantiate RAM)18:55
daveshahsomehow doing ASCII string processing in Verilog feels off18:56
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TD-Linuxmithro, nothing, I'm trying to interface to 1992 hardware :^)19:03
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mithrodaveshah: WTF :-P20:15
daveshahmithro: that's Lattice for you20:16
daveshahLayers upon layers of legacy that no one understands any more20:16
daveshahOh wait that's almost any company20:17
daveshahI'm not sure how much the core of Diamond has really changed since AT&T bought their NeoCAD license in '95 tbh20:31
daveshahThat then was sold with the ORCA FPGAs to Lucent, then Agere who were finally sold to Lattice20:32
daveshahMany of the primitives seem to originate from the ORCA days20:33
daveshahWhy am I now spending Friday night reading PDF manuals of FPGA flows from before I was born? What is wrong with me :P20:38
mithrodaveshah: sounds about right20:46
daveshahmithro: it's where the weird FF primitives came from. Letters were expensive back them20:54
mithrodaveshah: You say that - but one of the reason why unix commands are like 2 letters (like ls, cp, mv) is because typing on early terminals actually had very slow mechanical interlocks to prevent you pressing keys at the same time and causing shorts20:57
daveshahmithro: hehe20:57
daveshahI suspect the real reason is they were avoiding parameters for some reason, so they needed loads of different primitives20:58
daveshahAnd then they built on that with every new architecure over the last 25 years20:58
daveshahTbh, I'm both impressed as to how advanced things were back then and depressed as to how little has changed, compared to the silicon itseld20:59
tpbTitle: FPGA synthesis goes online - Electronic Products (at
daveshahCloud synthesis in 200021:02
daveshahCosting 15-60$ per run21:02
sorearnow the question is what is that per hour at the speed of the tools in 2000 :p21:06
daveshahThe biggest ORCA 3 part was about 6000 LUTs, which Yosys/arachne can do in maybe a minute or two max21:08
daveshaharachne's algorithms probably aren't much better than 2000 era, but might trade speed for QoR21:08
daveshahI can't imagine it would be more than an hour21:09
mithrodaveshah: You might underestimate how much faster computers have gotten since the 2000s :-P21:11
daveshahmithro: I'm going to assume it would be running on reasonably high end machines back then21:13
daveshahIt's hard to have a reference point because none of my uses of computers back then where really performance related21:14
daveshahMy Pentium III laptop certainly felt fast enough back then21:15
mithrodaveshah: 2000 was like ~Pentium 2 generation21:15
mithro400Mhz P2 -- 64mb sdram running at 100 mhz21:15
mithroMy 8088 felt pretty fast for a long time too -- definitely compared to my human abilities ;-)21:15
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sorear[yall have seen dan luu's input latency post?]21:20
qu1j0t3yes.... we have.....21:22
cr1901_modernErr, mithro, how old are you again :P?21:22
mithroGood question - Born 198321:22
cr1901_modernI mean, I have an 8088 (a few) but I certainly didn't buy it when it was new.21:22
cr1901_modernI thought you were closer to my age (1990)21:23
cr1901_modernAlso, tbf, I didn't learn how to program/_really_ play w/ computers until I was 18-2021:24
mithro8088 was my first computer and it was second hand from what at the time was our monopoly telco21:24
sorearqu1j0t3: i'd be surprised if you hadn't, but still remiss not to ask21:24
qu1j0t3we're still a bit confused by what he was measuring and unsure if anyone has reproduced the results.21:25
qu1j0t3anyone who's used transcontinental ssh knows that 200ms latencies are all but unusable21:25
soreardo you mean intercontinental21:26
qu1j0t3yes, inter-21:26
* mithro laughs at your 200ms -- Australia FTW!21:26
qu1j0t3who has time to duplicate his test rig? i suspect he has more free time than i do, so my rebuttal will probably never be written :D21:26
awyglemaybe it's actually 400 ms latencies that are all but unusable21:28
awygleand half comes from network and half from *other*21:28
qu1j0t3no, 200ms is awful21:29
mithroactually - latency isn't a huge problem - jitter is much worse21:29
qu1j0t3latency is a problem.21:29
qu1j0t3for me, anyway.21:29
TD-Linuxdan luu's post takes key travel into account21:29
qu1j0t3i know.21:29
qu1j0t3which seems pretty bizarre21:29
mithroHumans will adapt to a fixed length latency pretty easily21:30
qu1j0t3aren't we all typing on silly chiclet things nowadays? I mean, i'm not right now, i prefer proper keyboards21:30
qu1j0t3mithro: I don't want to adapt to 200ms. Really. And I don't think you would either.21:30
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qu1j0t3and i also don't believe we have, so luu's stuff smells funny.21:30
TD-Linuxno, I'm typing on a real keyboard. I imagine many are, the "mechanical" keyboards have even become popular with gamers21:30
awyglei'm typing on a rubber dome keyboard :(21:31
mithroqu1j0t3: Until they improve the speed of light, Australia -> US or Europe latency is always going to suck :-(21:31
awyglei actually _like_ chiclets but i don't even have one21:31
qu1j0t3i mean eventually arguments over Luu's piece may drive me to do my own measurements.21:31
qu1j0t3mithro: I'm aware from first hand experience :D21:31
awygleat least at work21:31
mithroqu1j0t3: Your a fellow Australian expat?21:32
qu1j0t3awygle: I have a 2012 MBP here with chiclets, i get used to it. I guess the Retina screen takes my mind off the keyboard.21:32
qu1j0t3mithro: Yes, actually :)21:32
mithroqu1j0t3: Ha, didn't know that21:32
awyglequ1j0t3: i have, like, _really_ bad RSI issues so the low travel and light touch of chiclets help me enormously21:32
TD-Linuxalso a lot of the views of old computer latency seem to have rose tinted glasses. For the early 90's machines I have, I get to watch it recompute palette all the time21:32
qu1j0t3mithro: (I assume you checked my hostmask, which is no longer indicative of my actual location)21:32
qu1j0t3awygle: *nod*21:32
awygle(this is also why i tweeted that thing about hating using shift)21:32
TD-Linuxand the apple II can't accept keyboard input while accessing the disk, like scrolling through a document21:32
awyglei certainly don't miss the computer going all "you just won solitaire" anytime i tried to do anything taxing21:33
qu1j0t3TD-Linux: haha, i am pretty sure the BBC Micro doesn't have that problem21:33
qu1j0t3TD-Linux: i don't recall any latency issues with machines i used in the 80s and 90s21:34
qu1j0t3TD-Linux: or indeed the ones i use today *shrug*21:34
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TD-Linuxqu1j0t3, yeah, well it has a real disk controller. the apple II has woz magic21:35
TD-Linuxalso the apple II has no interrupts at all.21:35
qu1j0t3the II was a bit dated by the time the Beeb came out.21:35
sorearthey don't need to improve the speed of light, just run gas/vacuum waveguides in a trench through the mantle21:35
qu1j0t3tell Musk, it might keep him out of trouble21:36
awyglena musk is a 10xer and that's only 3x21:38
qu1j0t3i think at 5x they should get a truman show dome21:39
qu1j0t3for the safety of the rest of us21:39
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