Tuesday, 2018-07-10

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jcllhi ! Newbie here. Can I find a free ASIC oriented techfile ?09:54
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jcllsorry. Just found the info in the doc. Thx10:01
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promachWhy am I having error "SBY 20:33:19 [async_fifo] base: ERROR: No such command: read (type 'help' for a command overview)" for this line "read -formal async_fifo.sv" ?12:39
promachI am already using latest symbiyosys git12:39
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daveshahpromach: you need the latest Yosys git for that too12:42
daveshahit was only added to Yosys a couple of weeks ago12:43
promachoh okay12:44
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promachdaveshah: it seems like https://github.com/YosysHQ/yosys#setup does not work with Ubuntu 18.0413:06
tpbTitle: GitHub - YosysHQ/yosys: Yosys Open SYnthesis Suite (at github.com)13:06
promachI am using kernel 4.17.413:06
promach./kernel/yosys.h:76:12: fatal error: tcl.h: No such file or directory13:06
daveshahpromach: are you sure `tcl-dev` is properly installed?13:07
daveshahlooking at the package contents it seemed /usr/include/tcl.h got moved to just /usr/include/tcl in newer ubuntus13:08
daveshahI don't use Ubuntu personally. Maybe ZipCPU is around, otherwise please open a GitHub issue (but removing the .h in the include directive should be a workaround for now)13:08
promachso, I will need to modify yosys.h then13:08
* ZipCPU starts reading backlog13:09
ZipCPUpromach: Do you have verific installed?13:09
daveshahZipCPU: tldr, Yosys seems not to build in Ubuntu 18.04 because of tcl.h13:09
ZipCPUThen yosys can't process system verilog files.13:10
promachproblem solved13:10
promach#  include <tcl/tcl.h>13:10
ZipCPUThat particular capabililty is part of the commercial version.13:10
promachdaveshah: use   #  include <tcl/tcl.h>13:10
ZipCPUThat would be why "read -formal async_fifo.sv" fails.13:11
promachZipCPU: yup13:11
daveshahZipCPU: read works with or without Verific13:11
daveshahit will autodetect and select the appropriate backend13:11
ZipCPUBut SystemVerilog only works with Verific13:11
promachI got to go now. anyway, make is building now13:11
ZipCPUSure, there are some supported non-verific pieces, but as a whole SystemVerilog requires Verific13:12
promachZipCPU: https://media.readthedocs.org/pdf/symbiyosys/latest/symbiyosys.pdf#page=913:12
ZipCPUOh, and one more ... I'm running yosys on Ubuntu 18 with no problems.13:12
promach[ 99%] Building abc/abc-6df139613:13
promachERROR: ABC directory is a hg working copy! Remove abc/ and re-run "make".13:13
promachmake  failed at the last step13:13
ZipCPUThat's an easy one13:13
ZipCPUFind the abc/ directory (I think it's at yosys/abc) and rm -rf it.13:13
promachI need abc13:14
ZipCPUYosys will then re-download abc from the github location, rather then the older mercurial based location13:14
ZipCPUThe problem is that the location of the abc repository moved.13:14
promachyosys make failed again, sigh. I will start rebuilding it again tomorroew13:17
* promach has to go now13:17
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promach_daveshah: both Ubuntu 18.04 and Arch Linux have problem installing yosys from git15:28
promach_make[1]: Entering directory '/home/phung/tmp/yaourt-tmp-phung/aur-yosys/src/yosys-yosys-0.7/abc'15:29
promach_make[1]: *** No rule to make target 'clean'.  Stop.15:29
promach_seems like abc has some changes upstream15:29
daveshahpromach_: I am building Yosys from source (not using AUR) on Arch fine15:31
promach_daveshah: you mean you "make && sudo make install"  ?15:32
daveshahpromach_: yeah, just trying with clean ABC now in case of ABC issues15:32
daveshahseems OK so far at least15:32
promach_ok, but to make things easier for future upgrade, I would email the AUR or ABC author about this. Do you think this would be a better idea ?15:33
promach_what do you mean by clean ABC ?15:34
daveshahpromach_: I deleted my ABC folder so Yosys cloned it again15:34
daveshahbut it still built fine15:35
daveshahI'd flag this as an AUR issue tbh15:35
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promach_daveshah: solved the AUR issue. I used the wrong AUR16:15
promach_I used yosys instead of yosys-git16:15
promach_For https://github.com/jbush001/NyuziProcessor/blob/master/hardware/core/synchronizer.sv#L38 , why am I having "SBY  0:07:34 [async_fifo] base: ERROR: Parser error in line synchronizer.sv:38: syntax error, unexpected $undefined" ?16:16
tpbTitle: NyuziProcessor/synchronizer.sv at master · jbush001/NyuziProcessor · GitHub (at github.com)16:16
promach_seems like yosys still does not fully support systemverilog16:20
promach_I have revert the coding style to verilog16:20
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jaafartinyfpga: are you around?16:50
tinyfpgajaafar: what’s up?16:50
jaafartinyfpga: it's Jeff from the meetup :)16:50
jaafartinyfpga: didn't know if you saw my email16:50
tinyfpgajaafar: i saw it, just hadn’t had a chance to reply yet :)16:51
jaafarI know you're busy shipping!16:51
jaafarOK good16:51
jaafarI was afraid you didn't read that address :)16:51
tinyfpgaShould finish shipping today, then I’ll be catching up on everything else16:51
jaafarTake your time and good luck16:51
keesjgood luck indeed!16:52
keesjI am going to give a presentation at work in a few days on the fpga work I have been doing. Being able to show them something like the floorplan https://knielsen.github.io/ice40_viewer/ice40_viewer.html really helps understanding. Thank you so much for the great work16:54
tpbTitle: ICE40 layout viewer (at knielsen.github.io)16:54
keesjI see this project having a huge impact16:55
keesjthe Yosys Open SYnthesis Suite16:55
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TD-Linuxoh wow I didn't actually know about that tool. this is way better to explain fpgas than using the xilinx p&r tool. I like how it can show all the spans17:08
keesjTD-Linux: to get details you have to zoom in a little https://pbs.twimg.com/media/C28FzIzWgAAzKDY.jpg for example17:10
* knielsen wrote it exactly to understand how his designs actually worked in the fpga, especially wrt. timing17:11
keesjwow .. thanks knielsen \o/17:12
TD-Linuxkeesj, yeah I figured that out. also you can make it draw them even zoomed out with the detail slider17:12
TD-Linuxfor c+d, a, ~a does it just recognize that lut pattern?17:13
knielsenyeah, there is a bit of logic to recognise common logic functions. I should really add more17:14
keesjI am currently looking into blinky17:14
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TD-Linuxlooks like vga has a lot of ands and nands.17:15
TD-LinuxI do like just seeing the lut bits though :)17:15
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keesjI think I might be trying to get to much in one hour ... Tristan Gingold presentatin at fosdem was also a pretty good 101 https://fosdem.org/2018/schedule/event/cad_fpga_intro/attachments/slides/2136/export/events/attachments/cad_fpga_intro/slides/2136/fpga_design.pdf on the basics (and I was using VHDL in my work hence.. kinda merging different things together)17:18
keesjon the blinky example (that is really quite simple) why don't I see a clock or similar going to the buffers? https://i.imgur.com/Lf7OdmY.png is this something implicit?17:23
knielsenkeesj: the clock is using one of the global nets (I think), and those are not implemented yet17:43
knielsenyou can see the clock entering in tile (0 8), from there it's routed to a global net and the rest is implicit in current code. The Icestorm docs has the details on how the global nets work17:45
knielsenwould be nice to see those global nets, though - might be tricky to find a way to draw them without drowning everything else though17:46
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keesjI don't see anything at (0 8) but I do see something at (0 16) called hwclk.17:49
knielsenright, that's the one17:50
keesjI think this is great enough to give a good start / idea on how things work. for myself I would like to understand a bit better but the presentation thursday so I don't have much time :P17:52
keesjtrying to reverse a bit https://i.imgur.com/JNDWTPo.png (but also need to watch football)18:04
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TD-Linuxon the ice40 explorer I noticed there are massive true/false nets. what's up with that?18:20
knielsenTD-Linux: I think I remember seeing that - I suppose it's just using a single LUT to provide a constant "1" and then routing that everywhere (and similar for "0")18:22
ZipCPUThere was an upgrade that was supposed to fix that.  Did it ever make it downstream?18:23
knielsenthough I can't now recall where it would need a constant 0/1 (it's been a while...)18:23
TD-Linuxthat looks like what it's doing. but... why?18:23
TD-Linuxcould just be that these are old bitstreams and a new yosys makes something better18:23
ZipCPUThe issue was that "1" and "0" had to be created, so they were created once and then routed everywhere.18:24
knielsenthe examples on ice40 viewer are definitely old bitstreams from a yosys probably several years old18:24
ZipCPUThe upgrade as I recall was supposed to remove the dependency of these constants on the various LUTs.18:24
knielsenaha, so for example in a random place in the vga example I see a counter doing "trans_x + 1", and using a constant "1" net for an X+Y LUT function. That could just be done with a single-input X+1 LUT function, without needing the constant "1" input18:27
knielsenmakes sense18:27
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keesjknielsen: what does18:54
keesjO meann in a LUT? is that OR?18:54
knielsendoesn't it just mean constant 0 output?18:54
keesjI don't know . sounds plausible18:55
keesjno I don't think so18:56
knielsensometimes only the carry output from a cell is used, and the normal output is just make constant zero18:58
knielseneg. see tile (23 19) in the vga example18:58
keesj(in the blinky example : counter[0] enters a block and (indeed possibly the carry goes to the next block)18:59
knielsenyes, the small wire vertically between the luts is the carry propagation19:00
knielsenfor some reason, apparently counter[0] and counter[1] flip-flops were synthesised/placed separately from the others. I guess one might need to check the icebox_explain output in detail to get all details19:04
knielsenthe exact logic for how LUT functions are rendered are found here: https://github.com/knielsen/ice40_viewer/blob/master/lutfunction.js19:04
tpbTitle: ice40_viewer/lutfunction.js at master · knielsen/ice40_viewer · GitHub (at github.com)19:04
knielsenhm, nifty bot...19:05
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keesjI think I was looking at it the wrong way https://i.imgur.com/JNDWTPo.png (the a +b  ) of counter 0 also acts as a flip flop). I will look at the js later19:13
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