Friday, 2018-07-06

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cr1901_modernmithro: Verilog mandates `ifdef SYNTHESIS if synthesis is taking place01:04
cr1901_modernin practice, everyone uses //synopsis translate_on/off01:04
cr1901_modern(which yosys complains about, and I've asked clifford for an option to remove those warnings, but to no avail :P)01:05
ZipCPU|Laptop.... but //synopsis translate ... is a message to the synopsis synthesizer, not to any other synthesizers.01:08
cr1901_modern//synthesis translate_on/off also works01:09
cr1901_modernIdk if it's strictly synopsys-only in practice that accepts those constructs (yosys does as well, but complains).01:10
cr1901_modernI do know I've almost never seen `ifdef SYNTHESIS, even though Verilog says this is the correct way to split simulation and synthesis sections01:11
cr1901_modernVerilog spec801:11
ZipCPU|LaptopSo ... just to play devil's advocate, should yosys be required to change because someone else's code is out of spec?01:13
ZipCPU|LaptopWouldn't it be more  appropriate to fix the code that's out of spec?01:13
cr1901_modernNo, yosys is correct, I just can't convince the rest of the world to change their own code or Verilog-generators :D.01:18
cr1901_modern^asking clifford for an option to suppress the warnings (b/c they are noise- I _know_ what I'm doing is morally wrong) was my backup when I realized the above lol01:20
ZipCPU|LaptopI suppose you could always patch yosys for this purpose, and maintain an out-of-tree patch ...01:23
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puddingpimpisn't it synopsys?03:43
puddingpimpalso does synopsys' synthesizer also support the standard way?03:44
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daveshahPlease don't use the old comments05:57
daveshahThere is literally no reason not to use ifdef synthesis05:58
cr1901_modernI wish Migen didn't generate them, but I'm guessing one of the 5 supported synthesizers only accepts the comments06:00
daveshahI doubt that, ifdef synthesis has been around for a good time now06:00
cr1901_modernISE supports it at least, based on a test (but I'm not about to grep for SYNTHESIS in a large manual)06:11
mjoldfieldIf you just want to suppress the warnings can't you pipe the output of yosys through a filter, or equivalently write a wrapper for the combo and invoke that ? It sounds better than maintaining your local version.06:14
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daveshahYou can just use -w regex already06:15
daveshahThat makes any warning matching a regex into a regular message06:15
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mithroThis might be a stupid question - but does yosys understand clock relationships to modules? I'm unsure what I mean by "understand" and "relationship" here :-P19:29
mithroBasically, I want to know what clock net is being used for a flip flop if a "data" net drives a flip flip19:31
mithrodaveshah: Do you know if that is possible? ^19:41
daveshahNo idea19:41
daveshahYosys has some handling of clock domains when it shoves stuff into ABC19:41
daveshahIt's probably also doable with some crazy select statement19:42
mithrodaveshah: Is this a clifford question?19:44
daveshahI'd say so19:45
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mithrodaveshah: what does "c:* %x:+[CLK] a:CLOCK=1 %u c:* %d" do? select all the things which have the CLOCK attribute right?20:37
mithroBut also maybe things which have 'CLK' in the name?20:39
daveshahmithro: It selects everything which connects to a port named CLK or has the CLOCK attribute set to 120:39
mithrodaveshah: Is there an easy way to filter that down to just top level ports? (IE any top level port which connects to a port name "CLK" or has the "CLOCK attribute set to 1") ?20:40
daveshahmithro: it might do it already, I'm not sure20:41
daveshahNeed to look at the syntax docs20:41
mithrodaveshah: Doesn't seem to...20:41
daveshahDefinitely doable though20:41
daveshahmithro: FYI
tpbTitle: Yosys Open SYnthesis Suite :: Command Reference :: select (at
mithroI'm looking at which took me too
tpbTitle: symbiflow-arch-defs/ at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
daveshahmithro: adding something like i:* %i to the end might work20:43
daveshahThat means push all the inputs to the stack (i:*)20:43
daveshahThen take the intersection of the two sets at the top of the stack20:44
mithrowholly crap is the select language complicated :-/ -- is this based on some standard or something?20:45
daveshahDon't think so20:45
daveshahBut tbh you could probably just use it to do place and route :P20:45
daveshahJust need to write a LLVM target for it20:45
daveshahNot sure if it's actually Turing complete20:46
daveshahBut I feel like it's not far off20:46
mithrodaveshah: adding 'x:* %i' does what I want I guess -- although I guess 'x:*' and 'i:*' should be the same mostly?20:47
daveshahmithro: yeah - I think clocks from VPR's point of view are inputs only?20:47
daveshahx:* includes inputs and outputs, if that matters20:48
mithrodaveshah: Not quite, they do have support for things like PLLs which have clock outputs20:48
daveshahmithro: but do they call them clock?20:48
daveshahmithro: great, use x:* then20:50
mithrodaveshah: What is "select -list {} %x* i:* o:* %u %i a:ASSOC_CLOCK={} %u {} %d" doing?20:50
mithrodaveshah: Looking for things which have an ASSOC_CLOCK={} attribute and ... ?20:51
daveshahmithro: Yeap. I think it also looks for wires connected to the same cell as the clock signal so they can be added automagically instead of requiring ASSOC_CLOCK to be specified20:53
mithroFrom clifford -- You should be able to do that with a select expression. Something like "net %co:+$dff[D] net %d %ci:+[CLK] n:* %i"20:53
daveshahmithro: yeah20:54
daveshahThat seems about right20:54
mithroIn answer to my question: I'm trying to figure out if a "data net" is going into a flipflop what the name of the "clock net" that is driving the flipflop20:54
daveshahI would start with the above expression from clifford and play about20:55
mithrodaveshah: That assumes my "flip flops" are all $dff objects right?20:58
daveshahmithro: yeah20:58
daveshahie you've run proc on a flattened elaborated netlist20:58
mithrodaveshah: So, 'c:* %x:+[CLK] a:CLOCK=1 %u c:* %d x:* %i' lists the clock signals -- how do I find all "models" that a clock is connected to a given name?20:58
daveshahmithro: too late for me to work that out right now20:58
cr1901_modernThat's the most readable perl I've ever seen20:59
mithrodaveshah: When I say "models" I probably mean "cells" right? -- IE black boxes / internal yosys objects like dffs / etc?20:59
daveshahmithro: yeah. What they will be depends on your yosys script21:00
daveshahIf you want models as in cells instantiated your Verilog, then you don't want to flatten21:00
mithrodaveshah: So I would start with selecting all the cells and the filtering out the ones which do not have a connection to the given net name?21:00
daveshahmithro: yes, probably21:01
mithroOkay - and the missing piece seems to be the21:02
mithrowhich lets me get cells connected to selected wires..21:02
daveshahYeah, %x is the magic glue21:02
daveshahNot sure if I really understand it either though21:03
mithroI don't quite understand why it has "expand top set <num1> times" -- but it seems like I can just use *21:05
daveshahYes, it depends if you want to repeat until nothing more is found or not21:06
daveshahYou can specify a number if you want a limit instead21:06
daveshahe.g. only one layer of hierarchy21:06
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mithrodaveshah: Ahh - it's for the hierarchy stuff - which doesn't make much sense after you have flattened?21:33
daveshahmithro: yeah, I think it will depend on that21:34
daveshahBut obviously the pb_type stuff needs hierarchy21:34
daveshahYou will likely need to sometimes use a flattened design with Yosys and sometimes nit21:34
mithrodaveshah: Yeah - That is enough context I can figure it out21:36
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mithroSo 'select -list w:*' gets me all the wires -- I'm confused why 'select -list w:*/INPUT_CLK' doesn't seem to return anything?23:09
mithro'select -list w:*INPUT_CLK' seems to work....23:10
mithroAny idea how "walk through" combinational cells like $and or $or cells?23:18
mithroIs that what %x* is all about?23:18
mithroWhen the docs say "expand top set" I took that to mean that it means the top of the stack, so when I do "select w:*INPUT_CLK %a %x*" why do I get OUTPUT_CLK?23:23
mithroHrm... I wonder if this is what the "input or output cones" means?23:27
mithroLooks like it...23:40
mithroLooks like what I want is called the "output cone"23:41
mithrodaveshah: Looks like what I want is "select -list w:*INPUT_CLK %a %co* o:* %i"23:44

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