Saturday, 2018-06-23

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promach_in smtbmc, what actually drives the always clocked block ?15:08
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janrinzehaving a strange problem. when I run yosys and arachne-pnr it seems that often i need to re run to get a working binary. are there tools to find out what happened and why some give failing binaries?19:00
daveshahjanrinze: are you running icetime? Sounds like a design that is failing timing, or possibly suffering from metastability19:06
janrinzeicetime reports that the result is properly within timing requirements.19:12
janrinzeany trick to track metastability?19:12
lutsaboundMetastability shouldn't keep the design from building19:14
lutsaboundAre you getting a binary both ways?19:15
janrinzeno of course not. but usually is caused by using different clock domains.19:15
janrinzeonly using one clock domain here.19:15
janrinzeand it is only 30 MHz.19:16
lutsaboundMetastability can also be caused by asynchronous inputs19:16
lutsaboundHow Are you generatinf your 30mhz clock?  Did you use icepll?19:18
janrinzeI use as many register latching as necessary. doing things in '[email protected](posedge clk)'19:18
janrinzeicepll for 120 Mhz and then divide by 419:19
daveshahIt's possibly the divide by four that's causing problems19:20
daveshah What board are you using BTW?19:20
janrinzeicoboard19:21
daveshahGreat, that doesn't have any known issues (some boards have dodgy PLL supplies causing these kind of issues)19:21
janrinzehx8k + 1MB SRAM board19:21
daveshahRoughly, what is your design?19:22
janrinzeoften re running arachne-pnr with -r fixes the issue19:22
daveshahYeah. That normally happens in cases where timing is a bit marginal19:23
janrinzedesign is a 16 bit CPU plus I/O (vga and keyboard.)19:23
daveshahAre you doing anything like negative edge clocks, etc, internally?19:24
janrinzeYes, as a matter of fact I do.19:24
daveshahicetime won't analyse them well19:25
daveshahI suspect the timing is marginal19:25
daveshahBest to try and run at a reduced clock frequency, and see if every design works19:25
daveshahIdeally using a clock straight from the PLL, without a divider19:25
janrinzeThis already is the reduce frequency .. used to be able to run at 36 MHz easily.19:26
daveshahPersonally I'd try and get everything running on the same clock edge19:26
lutsaboundMight need a timing optimiEd placer ...19:27
daveshahMy guess is it is the negative edge clocks causing the problems19:27
janrinzeyes, i understand. I will try to find an alternate solution.19:28
janrinzeWould it be smarter to clock everything with the pll at 120 MHz and add a 4 phase coding?19:31
janrinzethe code would be one hot.19:31
daveshah120MHz is really pushing the ice4019:31
daveshahPersonally I'd clock everything at 30MHz, positive edge19:31
daveshahThat's going to be by far the easiest approach19:32
janrinzeI had a design working very well at 65 MHz19:32
janrinzeother type of system though19:32
janrinzehx8k breakout board19:32
daveshahYeah, for a CPU I think that's really the upper limit19:33
janrinzei hear about 100MHz cpu designs on hx8k.. bogus, you think?19:34
janrinzecould very well be.. unless heavily pipelined system maybe?19:34
janrinzeAfter placement:19:35
janrinzePIOs       67 / 20619:35
janrinzePLBs       739 / 96019:35
janrinzeBRAMs      0 / 3219:35
daveshahMaybe, if you're really careful with design. VexRiscv goes up to about 80MHz, but in a small config with low instructions per clock19:35
janrinzei can do 1 instruction/clock mostly.19:36
janrinzeexceptions are the 2 word instructions , jumps, branches and of course multiply and divide.19:37
daveshahDo you have any pipelining?19:38
janrinzeif prefetching the instruction counts then yes ;-)19:38
daveshahOtherwise, sounds like 30-40MHz is probably a realistic target19:39
janrinzeload/store and jumps all will be a second stage.19:39
janrinzeand it runs of the external SRAM.19:39
janrinzeVexRiscv smallest (RV32I, 0.52 DMIPS/Mhz) that's what you mean, right?19:48
janrinzeit has a 32 bit bus to the block ram, i guess..19:48
daveshahYeap that's the config I was looking at19:55
daveshahNot having external ram makes things a lot faster and easier19:55
janrinzeat first I worried that the 16 x 16bit registers were the culprit but that seems to be hardly a problem19:57
janrinzetime sharing the bus with vga is no big issue either, it only needs to fetch a word once every 16 clock cycles.19:58
janrinzeSo i lose only 6.25 % of the bandwidth to the vga at [email protected]19:59
daveshahYeah, although the resulting multiplexers will increase the critical path delay20:00
janrinze10 ns SRAM.. that has a bit of leeway.20:01
janrinzewhen using 30 MHz the memory cycle is 33.3 ns20:01
daveshahYeah, but you have logic around that, bus turnaround time, etc20:02
janrinzepin delay is about 5 ns, right? so that still is more than 20 ns for the SRAM20:02
daveshahThere's logic delay too of course20:02
janrinzeyes but that is a lot less, at least according to icetime.20:03
daveshahBut remember that icetime does not take into account the SRAM delay, nor does it consider negative edge clocks properly20:04
janrinzetrue. I only use the negative edge for the write enable signal because it requires the address to settle first.20:05
janrinzei know that some FPGA have multi phase clock outputs. That could be a lot more stable.20:06
lutsaboundhttps://www.irccloud.com/pastebin/mjBSnKIv20:11
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)20:11
* lutsabound is not sure he likes his new phone20:11
janrinzelutsabound: the nwr signal is supposed to be low during the last half of the memory cycle. So only on negative edge would stretch it into the second half of the next memory cycle.20:16
janrinzedaveshah: it seems that icepll choses not to use global output but pllcore. would that affect the system adversely too?20:27
daveshahPossibly, but the core signal will be routed straight onto a global anyway20:28
daveshahSo the difference shouldn't be massive20:28
janrinzehttps://github.com/mystorm-org/BlackIce-II/wiki/PLLs-Improved this is about the blackice but it does have some info20:32
tpbTitle: PLLs Improved · mystorm-org/BlackIce-II Wiki · GitHub (at github.com)20:32
janrinzehttps://github.com/mystorm-org/BlackIce-II/wiki/PLLs-Advanced seems to be a bit more complicated but has a dual clock option.20:35
tpbTitle: PLLs Advanced · mystorm-org/BlackIce-II Wiki · GitHub (at github.com)20:35
janrinzefound this link too. there is a work-around mentioned here for the global clock buffers: https://www.mjoldfield.com/atelier/2018/02/ice40-blinky-hx8k-breakout.html21:36
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