Tuesday, 2018-06-19

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promachjust came across https://github.com/akzare/Async_FIFO_Verification . What do you guys think about the difference between yosys-smtbmc and UVM ?03:11
tpbTitle: GitHub - akzare/Async_FIFO_Verification: Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM. (at github.com)03:11
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mattvennZipCPU_: I didn't really understand your tweet about the 32bit multiplies08:23
mattvennIn my FFT implementation I just did a <= b * c;08:23
mattvennwhich seemed to work OK08:23
mattvennis it that you can write a more optimised multiplier than yosys can infer if you know what type of numbers the multipy will be handling?08:24
daveshahmattvenn: Yosys will always infer a single-cycle multiply if you do that08:28
daveshahZipCPU_ wanted a multi-cycle multiplier08:28
mattvennso that it could fit with a pipeline or some other multi cycle logic?08:28
mattvennor uses less LUTs?08:29
daveshahin this case, the idea is one value is only needed every 32 cycles (for example), so far fewer LUTs are needed compared to a full single cycle multiplier08:35
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maikmertenhi there, I'd like to use the SRAM on my icoboard, for which I'd need a tristate in/outputs for the data lines. Some while I ago, I think I read that yosys only has limited tristate support. Is there some hint on what "limited" means in this case? I'd like to avoid instantiating the I/O manually if possible.15:19
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daveshahIt is generally best to instantiate IO if you want anything fancy15:24
daveshahThe most basic tristate pattern hopefully works, a fix was even pushed a few hours ago15:24
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maikmertendaveshah, thanks16:12
maikmertencompletely unrelated: does anybody know how iCE40 HX devices compare against entry-level stuff from Altera (e.g., Cyclone IV) or Xilinx (Spartan?) speed wise? The RISC-V SoC I'm developing for fun has an icetime estimate of somewhere between 49 to 56 MHz, depending on placement luck. A similiar design usually went to ~ 80-90 MHz in Cyclone IV and I wonder how the FPGAs come into play here.16:15
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mattvenndaveshah: thanks16:34
sorearicestorm is known to be a fair amount worse than lattice tools at timing optimization16:34
maikmertenas far as I can see it's not timing driven, just tries to keep routes short - which of course strongly correlates16:38
daveshahmaikmerten: the problem is, different routes have different "importances" in timing16:39
daveshahif a route is part of a timing path with lots of cells, it must be shorter than one in a path with few cells16:39
awyglearachne also doesn't prioritize the longest route or anything like that16:39
awyglei wonder if switching from HPWL to QWL would give better timing results...16:40
maikmertendaveshah, indeed - yeah16:40
daveshahawygle: it's something to investigate once we have a better framework for doing these kinds of experiments16:41
awygledaveshah: yup. although hopefully we can use better models at that point.16:41
awygleQWL is a one-function change to arachne16:41
awygle(to first order anyway)16:41
maikmertenjust to be clear: I'm *very* happy with the whole icestorm experience and the synthesis results are more than just fast enough for my hobby applications16:42
maikmertenalso the tools are fast... from "make clean" to a bitstream file including timing analysis in < 30 seconds on my Ryzen 270016:43
awyglemaikmerten: glad to hear :) you didn't come off as unhappy, we just always want things to be better16:43
maikmertenas for the hardware itself: iCE40 seems to a simple, yet reasonably "fresh" design on 40nm, so at least from that vantage point it shouldn't be at an disadvantage compared to e.g., Cyclone IV16:45
awyglemy understanding is that the altera LABs are much more powerful, and that the ice40 is generally optimized for power consumption rather than speed. but i'm not familiar with cyclone iv at all.16:47
maikmertenyeah, seems that Lattice is pushing the power aspect most16:48
awyglethis is most clear with the UltraPlus, which is ~half the speed of the LP16:49
maikmertenI'd guess they're pushing that as "glue logic" for mobile applications16:50
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maikmertenseems yosys has no problem instantiating tristate buffers for my application: https://pasteboard.co/HqDZ6rg.png17:23
tpbTitle: Pasteboard Uploaded Image (at pasteboard.co)17:23
maikmerten(code: https://pastebin.com/hJUDGMtg - completely untested, of course. Some weirdness because of my data bus being 8 bits wide, while the SRAM is 16 bits wide)17:24
tpbTitle: [VeriLog] module sram64kx16_wb8 ( // Wishbone signals input CLK_I, input STB_I, - Pastebin.com (at pastebin.com)17:24
ZipCPUShouldn't they then be connected to SB_IO's?17:25
maikmertenI didn't yet throw things into my toplevel, so it's just this single file with no pin assignments17:26
daveshahZipCPU: arachne_pnr inserts SB_IOs, not Yosys17:26
awyglethat's a bit weird. arachne maps yosys TBUFs to SB_IOs?17:29
awyglehuh. that seems firmly in the realm of synthesis to me. but i'm sure there's a good reason17:29
ZipCPUYeah, that was my thought to --- that seems like a Synthesis task: mapping logic to generic resource types within a device.17:32
daveshahyeah, there's no real reason it couldn't be done in Yosys17:34
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develonepi3Hello All anyone interested in bare metal for the RPi & icoboard see https://gist.github.com/develone/e8de5745e1f8daa979b789ad7bd366e1#file-yosysinfo-txt20:23
tpbTitle: notes.txt · GitHub (at gist.github.com)20:23
develonepi3tpb yes there is a file yosysinfo.txt20:46
develonepi3see https://github.com/develone/Ultibo_Projects/blob/master/fpganetport/RPi3/Srv.lpr & https://github.com/develone/Ultibo_Projects/blob/master/fpganetport/RPi3/ufpga.pas20:51
tpbTitle: Ultibo_Projects/Srv.lpr at master · develone/Ultibo_Projects · GitHub (at github.com)20:51
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