Monday, 2018-06-18

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azzizi_21:17 <azzizi> I had a question .........can I create a script using matlab or any other language and create a modified RTLIL and can Yosys work with that ? I mean can I input the modified RTLIL ?  21:20 <daveshah> azzizi: yes, of course, but I personally wouldn't want to try and parse and generate RTLIL in Matlab  21:20 <daveshah> Probably be faster to learn C++  21:23 <daveshah> The relevant command is read_ilang though  21:24 <da15:45
azzizi_21:24 <daveshah> The Json format is also worth looking into as a way of processing designs in another language15:46
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azzizi_<daveshah> thanks ...I am thinking about python ...but any idea how do input the newly created RTLIL to Yosys it can work with the new RTLIL and get the backends work on it?15:47
daveshahazzizi: you can use read_ilang15:48
daveshahbut ilang is not a stable or supported external format, its primarily for Yosys debugging15:48
daveshahI would really recommend looking at JSON instead15:48
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azzizi_<daveshah> For my work, I think I could work on RTLIL's fine that it's not supported..could you elaborate on "not stable" ?15:51
daveshahazzizi_: there is a risk it could change in new Yosys versions15:51
azzizi_SO the rtlil needs to be transferred to JSON first and then worked on it ?15:53
azzizi_dang ..never thought of this15:53
daveshahyou should use "read_json" and "write_json" in Yosys15:53
daveshahthis is the current recommended interface for external tools working with Yosys15:53
azzizi_read_json converts a verilog source code into json ? and write_json converts json to verilog netlist?15:55
ZipCPUwrite_json converts the internal representation to a JSON output file.15:56
ZipCPUread_json reads the given JSON file and initializes the internal structures with the information found within it.15:56
ZipCPUNeither file translator works on Verilog.  Verilog may however be ingested into yosys, and then converted to JSON.15:57
azzizi_<ZipCpu> By ingested, do you mean using read_verilog and then write_json16:01
ZipCPUPretty much, plus any transformations that have taken place in between.16:01
azzizi_<ZipCpu> Can I go back from json to verilog netlist....  like read_json and then write_verilog?16:03
ZipCPUIt'll be just like it was when you tried read_verilog followed by write_verilog.  The result might look nothing like the input, although it should be logically equivalent16:04
azzizi_Basically I want to modify an intermediate representation ....add some stuffs an then input the modified representation into Yosys16:04
ZipCPUYou are likely to find JSON useful for that purpose.16:06
azzizi_JavaScript Object Notation?16:06
ZipCPUIs that what JSON stands for?16:07
azzizi_yeah I googled16:07
azzizi_Am I right ? I wish the RTLIL were stable lol16:08
azzizi_Wouldn't have to look into JSON any more16:08
ZipCPUI just refactored yosys's JSON parser into another piece of software for another purpose.  It wasn't really all that hard.16:09
azzizi_In the manual I dont see any read_json16:17
azzizi_read_json reads the given JSON file and initializes the internal structures with the information found within it.16:21
azzizi_so can I assume it transforms Json format to RTLIL?16:21
azzizi_Sorry for asking too many questions lol16:23
ZipCPUYes, you may assume that.16:28
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azzizi_I have seen the JSON format, but it seems it doesn't have all the  information flow there unless I am mistaken..netlist information is there ..but not the data flow17:26
awyglei'm not sure what you mean by data flow in this context17:54
tpbTitle: Help please - Album on Imgur (at
azzizi_For this source code, data flow would be the lines state<=1 and stuffs like that17:57
azzizi_I converted the RTLIL to json17:57
azzizi_But not being able to find the JSON lines representing the dataflows17:58
azzizi_Please help18:06
ZipCPUazzizi_: What do you mean by "data flow"?  What specifically are you looking for?18:06
ZipCPUOh, yeah, one more thing azzizi_: Look at the *last* main element in the JSON file to find your logic.18:07
ZipCPUWith the JSON file's I've looked to date, the other items don't describe your logic, but often rather the capabilities of the elements in your system.18:07
azzizi_So are you saying not all the information will be there in Json file ?18:08
azzizi_I am pretty sure RTLIL has everything ...but if JSON doesnt have everything I have no other options but to work on RTLIL but as this is not stable I am in a dilemma18:09
ZipCPUNo, the other way around: you may have more information in the JSON file than just your design.18:09
daveshahazzizi_: the JSON file contains an elaborated version of your design18:10
daveshahYou might want to run proc or even prep before generating it18:10
daveshahThen the data flow should be included, albeit converted to a netlist18:10
tpbTitle: 'Please see' | (at
azzizi_Please check this Json output dataflow18:13
azzizi_the source code for the previous imgur18:13
daveshahazzizi_: run `proc` before generating the json18:15
daveshahyou can already see the add and equals cells. Other cells for the registers etc will be created when you run `proc`18:15
azzizi_Thanks it worked now ...but sadly it is at the netlist level ..with the mux and registers added which I don't want ...I need to be able to edit the code at higher level than that ...changing the RTLIL would be perfect for me18:19
azzizi_But it may change in future and not stable so  Ihave to rethink some stuff18:19
daveshahYeah, in practice it sounds like RTLIL will be OK. I doubt there will be any breaking changes, but its also not really guaranteed18:21
azzizi_what is not guaranteed ?18:21
daveshahThat RTLIL Ilang will be a stable interface forever18:22
daveshahBut it's almost certainly fine. Officially though that kind of stuff should be done using the C++ interface directly18:23
azzizi_Thanks, May I know if you know of any ways to input the modified RTLIL (that I get from the script I will write) into the Yosys steps so I can work with it in the latter steps of yosys with the new RTLIL in the Yosys ...if I write write_verilog then it will give me verilog netlist18:24
daveshahYes, use read_ilang18:24
azzizi_Why not read_rtlil ?18:29
azzizi_Sorry just asking18:29
azzizi_I thought ilang was a textual representation of rtlil so they must be the same thing18:29
daveshahRTLIL is the name for the internal data structures representing RTL. "ilang" is the name when it is dumped in textual form18:30
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azzizi_SO in the picture shown in the manual, it is depicted we can work on RTLIL writing any pass not ILANG18:51
azzizi_So the modified RTLIL has to be in ilang form for me to be using the read_ilang command?18:54
daveshahI don't understand your question18:55
daveshahilang is the only external direct form of RTLIL18:55
tpbTitle: Help - Album on Imgur (at
azzizi_The picture shows passes work on RTLIL it has all the information...I know I can get the RTLIL form of any source code by read_verilog -dump rtlil ................but if I want to do the reverse script will modify rtlil and  input the modified RTLIL into yosys I can't use read_rtlil or something like that ?19:13
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azzizi_Why do I have to work with ilang19:14
daveshahRTLIL is the name for the external data structures. If you want to work with RTLIL directly, use the C++ interface. Otherwise ilang is the text form of RTLIL for external use19:15
azzizi_May I ask the commands for the commands for getting Ilang representations of any verilog? and also Ilang to verilog netlist?19:18
azzizi_Thanks ...the last sentence explained a lot19:18
daveshahread_verilog x.v; write_ilang x.ilang19:19
daveshahread_ilang x.ilang; proc; write_verilog x.v19:19
daveshahThe proc may or not be needed in the latter case19:19
azzizi_Depending on if I use 'always' ?19:20
azzizi_Thanks a lot19:20
daveshahSometimes it will work directly with write_verilog19:20
daveshahBut proc is safer19:20
azzizi_proc seems to take everything in the netlist level though ...adds mux and registers ..too low a level to work for me19:21
azzizi_although I have not seen19:21
daveshahazzizi_: I am curious, what exactly are you trying to do that must be done at Verilog source level rather than on an elaborated netlist?19:44
azzizi_<daveshah> It's an amendment of some sort of the source information so as to not let the IP attackers lives be more difficult19:50
azzizi_let the *19:50
daveshahazzizi_: sounds very interesting19:50
azzizi_yeah it is ...thanks19:51
daveshahI know there are some people doing this kind of research with Yosys. Might be worth getting in touch with them?19:51
daveshahI think Christian Krieg at TU Vienna is one of them19:52
azzizi_May I ask how do I contact him ?20:04
azzizi_That would be of great help20:04
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daveshahDon't have contact details I'm afraid. But his Twitter is
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azzizi_Anyone has any verilog code for which Ilang and rtlil is different ? for me allof my example codes RTLIL and Ilang are same21:05
daveshahazzizi_: I am not sure if they will ever be different, ilang is the text representation of RTLIL, the only difference is in the naming of the command generating the output21:07
azzizi_Thanks again deveshah21:10
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