Saturday, 2018-06-16

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promach_Can SymbiYosys support wildcard files selection yet ?01:38
promach_and does Yosys support any automated bug insertion (mutation) methodology ?01:52
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gyroninjaHi, I'm having trouble synthesizing a design I've made. It removes all the cells during optimization leaving me with 0 cells total in the end. This is likely me to either using yosys wrong or verilog wrong as I'm a newbie at both. I've created a small test program which exhibits the behaviour I'm talking about: If I use use verilator to simulate the design, it seems to work05:45
gyroninjafine (the data output is toggled).05:45
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gyroninjaI've also tried on both version 0.7 and the latest from git05:47
ravenexpdata is not a reg05:51
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ravenexpyou can't parallel assign a value to a wire05:52
ZipCPUYou might also wish to look into the "show" command.  It works great on small designs to illustrate a logic flaw, but ... can be difficult to use with really large designs.05:57
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promach_Why do I have this error when I try the code at ? note that I have installed avy16:36
tpbTitle: Ubuntu Pastebin (at
daveshahpromach_: what happens when you type just avy at the shell?17:07
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promach_daveshah: it seems like I did not install it properly17:13
promach_let me do the installation of extavy again tomorrow17:14
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gyroninjaAfter messing around with it for a while, I still haven't been able to figure out what I did wrong. I tried declaring my output as reg and switching = and <= around, but it didn't help. I did notice that if it seems to work fine if I use an if statement / conditional operator to set my output instead of from an array. <- Is my broken code that doesn't generate any cells. If20:13
gyroninjayou uncomment the commented line and comment the one below it, it seems to work.20:13
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gyroninjaAlso here's the BLIF files that both outputed
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ZipCPUgyroninja: Start at the top again ... what are you tring to do?21:08
ZipCPULooking over your code, I noticed you declared an array of one element: reg [0:0] array[2];21:09
ZipCPUDid you mean to do that, or were you trying to do: reg [0:0] array [0:1]; ... an array of two elements?21:09
ZipCPUAlso, as a matter of general practice, most synthesizers don't recognize arrays from block RAM elements if anything else is with them within their always statements.21:10
ZipCPUHence, I think you wanted: always @(posedge clock) data <= array[index]; always @(posedge clock) index <= !index;21:11
ZipCPUI just implemented a multiply algorithm to implement
tpbTitle: Binary multiplier - Wikipedia (at
ZipCPUA very strange algorithm to debug.  I think I misread the description incorrectly several times over.21:13
* ZipCPU now has it working through an exhaustive simulation via verilator.21:13
gyroninjaZipCPU: I want to essentially look up a value from the array21:14
gyroninjaand assign it to the output21:14
ZipCPUYeah, you have your array declared incorrectly.21:14
gyroninjaIsn't it an array of 2 elements though?21:14
gyroninjaof 1 bit each21:14
ZipCPUNot if you declare it as: reg [0:0] array [2];21:14
ZipCPUYou need to declare an array of two one-bit elements as: reg [0:0] array [0:1];21:15
gyroninjaDoing it the way I've been doing it works fine with Verilator21:16
gyroninjabut yet doing it your way makes it generate cells21:17
gyroninjaand fixes the problem21:17
ZipCPUAhm ... I doubt it was really working with Verilator.21:19
gyroninjaIt was though21:19
ZipCPUIf you dig into code like that, you'll often find Verilator reading from unallocated memory21:19
ZipCPUWhere it gets really bad is when you try to write to that memory, and then overwrite something on your stack or something21:19
gyroninjaWell something to point out is that it at least recognized it as an array21:20
ZipCPUAbsolutely!  You told it that it was an array of one element.21:20
gyroninjaIf I tried to assign into an element beyond the second element it would warn me and not compile21:20
ZipCPUThen, you initialized two elements that weren't in the array.21:21
gyroninjaIf I declare it with [2] and try to assign to array[2] the warning I get from verilator is: "%Warning-SELRANGE: test.v:13: Selection index out of range: 2 outside 1:0"21:23
gyroninjaNotice how it seems to be interpreting the 2 as 1:0 for me21:23
ZipCPUNot quite what I was expecting--what does the C++ generated code look like?  Should be easy enough to interpret.21:24
gyroninjaVtest.cpp: Vtest.h:
ZipCPUCheck out lines 73-83 of Vtest.cpp for discussion21:28
ZipCPUThat's what's implementing this logic ... if I've read it right (and I'm trying to read quickly)21:29
ZipCPUThe index is anded with one to create the new index, but it is also referencing the array like that as you suggested.21:30
ZipCPULooks like that might be a bug in Verilator.21:30
ZipCPUVerilator *should've* taken the index, subtracted two from it, anded it with 0, and then used the result to look up the array value21:31
gyroninjaI'm not following21:33
gyroninjaIf you anded it with 0 wouldn't it always be 0?21:34
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gyroninjaIt seems to be valid syntax regardless22:09
gyroninjaI checked the BNF and it seemed to check out22:10
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