Tuesday, 2018-06-12

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puddingpimpnice, I took a second look, and managed to build yosys on FreeBSD with only one patch11:37
puddingpimpin verilog_parser.y, FreeBSD's version of bison-2.7.12 from 2013 can't handle %define parse.error verbose11:37
puddingpimpcommented it out and the whole thing built11:38
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puddingpimpFreeBSD won't take bison 3 for license reasons, but it's probably installable from a ports11:42
puddingpimpyea, devel/bison is 3.0.411:44
cr1901_modernDoes bison have a define for the OS you're running on? I believe the idea is yosys should run without _requiring_ any external deps on each OS11:45
* cr1901_modern might be wrong11:45
cr1901_modernI should also test a compile on NetBSD sometime soon, but right now I only have a RPi 1 running it11:46
cr1901_modernyosys _should_ compile, but it'll take days when it has to go to swap lmao11:46
puddingpimpI'm not familiar with bison, I just did the minimal research to figure out why it was failing11:46
puddingpimpprobably the right ifdef bracket, if that's what you're suggesting is bison version >= 3 (however that is expressed)11:47
cr1901_modernyes that11:48
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puddingpimpsince it probably should use define parse.error verbose if the user has devel/bison installed (as it gives better debugging when hacking on the parser)11:48
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cr1901_modern%require "version" is the best I can find, but that exists w/ an error if you don't have the correct version11:50
puddingpimpbeats me, I can't even figure out how to do a conditional compile in bison12:21
puddingpimpI wanted to submit a patch, but I can't figure out the right solution, so I'll proceed with the works-for-me approach of commenting out that line12:23
puddingpimpnote, the FreeBSD install instructions in README do mention pkg install ... bison ... so if you just follow the instructions like I didn't, it should just build12:27
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cr1901_modernahhh I see12:30
puddingpimplast time I tried building on FreeBSD, there were no instructions, and I think I had more build errors, or were just less pereserverent12:30
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promach_awygle: for your UART, did you manage to pass induction depth of 10 if CLOCKS_PER_BIT is 8 ?14:31
promach_what is your induction depth during test ?14:31
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azziziHello ! Can anyone lpease checkout the imgur link: https://imgur.com/a/xs167on19:03
tpbTitle: Help please - Album on Imgur (at imgur.com)19:03
azziziMay I know why initially there are subsequent attribute wire attribute wire lines ?19:04
daveshahazzizi: in this case, the attributes say which source line each wire came from19:05
daveshahThey are intended for diagnostics, primarily19:05
azziziAnd may I know the meaning of wire width 32 $add$new.v:22$7_Y19:09
daveshahThat simply means a wire of width 32 and name $add$new.v:22$7_Y19:10
daveshahThe name is merely an internally generated identifier19:10
azziziLine 22 has 'count'...is it the identifier for count ?19:14
daveshahIt might be another part of the logic generated by or related to that line19:15
daveshahPersonally I'd avoid trying to parse the Yosys identifiers19:16
azziziMay I know why? RTLIL has all the information of the source code and probably I will have to parse the identifiers to know about the transitions / control flow19:18
azzizi<daveshah> you see anything wrong with my plan?19:31
daveshahI don't think identifiers are considered stable19:31
daveshahYou should be looking at src attributes to get file and line information19:32
daveshahAnd cells for anything functional19:32
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azziziThanks <daveshah>.........could you please look at the imgur...... "attribute \src "new.v:22"   cell $add $add$new.v:22$7"  these two lines in the RTLIL and the subsequent definitions of parameter and connect..any idea what they mean?19:55
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daveshahThis instantiates a $add cell (the text after `cell` is the cell type and then name)19:56
daveshahThe parameters specify the port widths and signedness of the add operations19:57
daveshahThe connect tell you what the nets the ports of the adder connect to19:57
daveshahA and B are the adder inputs and Y the output19:57
daveshahThe operation here is: $add$new.v:22$7_Y = count + value19:58
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awyglepromach: i haven't looked at that in months, but apparently i was using 20020:26
awyglewith 16 CLOCKS_PER_BIT (which is OVERSAMPLING in my code)20:27
awyglebasically for that test i selected a depth that included the whole character20:29
awyglebut that might have been for "cover" purposes, not for induction - might have been able to pass a shorter length, i don't remember. you can try it out easily though.20:29
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