Monday, 2018-06-11

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mithroAnyone know what the .SEQ_MODE parameter in the output from icetime mean?00:37
* cr1901_modern doesn't know the answer to any of those questions :/00:42
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mithrohey cr1901_modern00:58
cr1901_modernhello mithro, how's it going?00:58
mithrocr1901_modern: Super frustrated because I'm super close to getting things working00:59
cr1901_modernmithro: Hey me too! Except the super close to getting things working part00:59
cr1901_modernThat part has evaded me00:59
cr1901_modernI still have crashing lm32 bitstreams on tinyfpga, and I don't know why. I even made a repo documenting crashes01:00
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mithrocr1901_modern: At least reproducible is good!01:15
mithrocr1901_modern: Want to look at my problem instead then? :-P01:15
mithrocr1901_modern: I'm trying to figure out why my icestorm HLC output is not logically equivalent to the input01:16
mithroNot quite sure what it stands for01:17
mithroit's a high level description format that icestorm uses01:17
mithrocr1901_modern: You can seen an example here ->
tpbTitle: Ubuntu Pastebin (at
cr1901_modernWell, if you're intimately familiar w/ ice40 internals, your problem doesn't sound all that fun either.01:18
cr1901_modernI wonder if there's a(n easy) way to move _just_ one SB_LUT to another location in a design, and then recompile the result to a valid bitstream01:19
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xerpiI'm trying to use this NAND2 gate:
tpbTitle: yosys/cmos_cells.sp at master · YosysHQ/yosys · GitHub (at
xerpithe problem is that if I set A to Vdd and B to Vss, then I get "doAnalyses: Too many iterations without convergence"08:23
xerpiI'm using ngspice btw08:23
xerpiit looks like there's a problem in the node M34 (the one between the nmos transistors in series)08:23
xerpiany idea what's going on?08:23
xerpiit looks like it's because I'm using different transistor models08:30
* sorear hasn't touched spice in years08:30
daveshahgosh, this takes me back to when I was writing a circuit simulator08:33
daveshahjust curious, what if you tie A and B via resistors rather than directly?08:34
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xerpidaveshah, doesn't seem to work08:55
daveshahxerpi: not sure if I can suggest anything more either, haven't touched SPICE for a while either08:56
xerpino worries, I think it's because my capacitance at the output is too small08:57
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mithrodaveshah: Did something change in yosys recently -- I seem to have lost the ability to get SB_LUT4s in the output?14:47
mithrodaveshah: Oh - a LUT1 isn't mapped to a SB_LUT4 ?14:48
daveshahmithro: What is your code?14:49
tpbTitle: symbiflow-arch-defs/lut.v at 4mcmaster · mithro/symbiflow-arch-defs · GitHub (at
mithrodaveshah: It gets converted to a wire rather than a LUT14:52
daveshahOf course it is a wire14:53
daveshahThat statement is in no way a LUT114:53
mithrodaveshah: What is a LUT1?14:57
shaprlookup table 1 ?14:57
mithrodaveshah: Actually - what is the difference between a LUT1 and a wire?14:57
daveshahA LUT1 could be an inverter too14:58
daveshahOr const 0 or 114:58
daveshahIf you want a LUT instantiate a LUT14:58
mithrodaveshah: Is there a specific "LUT1" primitive in Yosys?14:59
daveshahThere might be an internal one, but you should just use an architecure primitive14:59
mithroarchitecture primitive? As in the SB_LUT4?15:00
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tpbTitle: Snippet | IRCCloud (at
mithrodaveshah: Should that work?15:03
mithrodaveshah: It doesn't :-(
tpbTitle: Creating a SB_LUT4 with unconnected inputs causes a C++ exception · Issue #567 · YosysHQ/yosys · GitHub (at
daveshahmithro: clifford will look at it15:08
daveshahBug in the ice40 optimisations15:08
mithrodaveshah: Yeah15:09
mithrodaveshah: This LUT implementation kind of looks weird...15:10
tpbTitle: yosys/simlib.v at 0d636964b81ed5db4a7031a24c4b04e3bc879ad5 · YosysHQ/yosys · GitHub (at
daveshahNot sure, I think it's reasonable15:10
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GroomblecomQuestion about iCE40hx1k devices: how do I write verilog to synthesize a SB_WARMBOOT?15:12
GroomblecomAs is frequently the case, I found what I was looking for after asking for help:
tpbTitle: icestorm/examples/icemulti at master · cliffordwolf/icestorm · GitHub (at
GroomblecomFollow-up question: according to the datasheets, BRAMs are not refreshed when you warmboot, unless you provide initialization data with the new config image. How do I ensure my verilog in each design gets the same BRAM?15:29
GroomblecomSo that I can, e.g. compute a buffer with one config image, and then warmboot to a second image that processes the first image15:30
Groomblecom*processes data from the first image15:30
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mithrodaveshah: Any idea why icebox_vlog didn't combined the inputs here?15:43
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daveshahmithro: Verilog?16:29
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