Sunday, 2018-06-10

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cr1901_modern(Rhetorical) Is it normal for "icebox_vlog -l" to get the pin numbers completely wrong?13:13
cr1901_modern_none_ of them match the pcf13:13
cr1901_modernOh I see, my icebox_vlog is too old13:17
daveshahyes, just fixed that  a few days agp13:20
daveshahyou can now tell it the package13:20
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cr1901_modernAnd post-PAR synth _also_ suggests my design should work13:30
cr1901_modernfabulous. I have no way to debug this13:30
cr1901_modernI'm really sick of getting in over my head. What am I supposed to do, decap and read the voltages w/ a FIB?13:31
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tinyfpga_cr1901_modern: do you have your project online anywhere?15:42
cr1901_moderntinyfpga_: Yes, I do. Lemme push changes15:42
cr1901_modernI have one last thing I can try before I'm truly stumped. But of course it's the most effort15:42
cr1901_modernI'll do what ZipCPU does and put a logic analyzer inside (or something that can control the clock one cycle at a time)15:43
tpbTitle: GitHub - cr1901/misoc-lm32-sim: Testing LiteX LM32 SoCs for bugs using Verilog simulation. (at
cr1901_moderngit submodule update and then "make TARGET=tinyfpga-soc-no-trigger"15:46
cr1901_modernYou will get 3 .vcd files as output- one pre-synthesis, one post-synthesis, and one post-PAR15:46
cr1901_modernI never get uart output when I load this bitstream to FPGA15:46
cr1901_modernbut it works in all simulations15:46
tinyfpga_cr1901_modern: ok, I’ll try and take a look at it today15:48
tinyfpga_cr1901_modern: which board are you using? A B2 or BX prototype? I can remember what I sent your way.15:54
tinyfpga_cr1901_modern: what were you using for UART to USB?15:54
cr1901_modernI broke out pins 5 and 6 for another UART15:54
cr1901_modern(for now anyway)15:54
tinyfpga_cr1901_modern: what device where you connecting to the B2 to perform UART to USB conversion?15:57
cr1901_modernprolific FTDI cable15:58
tinyfpga_cr1901_modern: can you send a link to the product page?16:06
tpbTitle: USB to TTL Serial Cable - Debug / Console Cable for Raspberry Pi ID: 954 - $9.95 : Adafruit Industries, Unique & fun DIY electronics and kits (at
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mithroDoes anyone know if the models output by icetime have implementations anywhere?23:15
mithroanyone know if there is a way to stop yosys rotating the inputs on of a lut when outputting to a blif?23:38
mithroI'm assuming it is happening because of "synth_ice40 -nocarry; ice40_opt -unlut; abc -lut 4"23:39

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