Thursday, 2018-06-07

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mithroIs there a way to prevent yosys from "optimizing" a design / lut away?00:17
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awygle(* KEEP *) i think?00:21
mithroawygle: yeah - actually that seems to have worked...00:27
awygleHTH lol00:29
mithroawygle: Do you know what the best way to create a LUT5 in the ice40 is?00:31
cr1901_modernProb from 3 LUT4s?00:43
puddingpimpcan probably compress into 2 LUT4s in many cases00:54
awyglemithro: I'm not aware of a better way than "write one in Verilog"00:55
mithroawygle: I was more interested in how you might pack the needed structures for a LUT5 together into a cell for an efficient design00:57
awyglemithro: ah. No particularly good ideas.01:04
mithroawygle: Like I feel like the LUT cascade or something might be useful01:04
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mattvenncool interview with Clifford Wolf here:
mattvenncool interview with Clifford Wolf here14:55
mattvennlots of interesting stuff, and last 30 minutes is all about formal verification14:55
awygletinyfpga was also on amp hour recently, which was cool15:25
awygleand Michael Ossman shouted out azonenberg during his segment15:26
awyglewe gotta get some open fpga folks on, the podcast I actually listen to :-P15:27
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mattvennI only just heard about that one16:25
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azzizi_What should be the sequence of commands to convert verilog to bench files ..?17:09
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azzizi_Can I upload any picture here ?17:12
ZipCPUNo, but you can upload a picture to and post the link here.17:13
ZipCPUA picture might help to understand what it is you want to do.17:14
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azzizi_Please check :
tpbTitle: Imgur: The magic of the Internet (at
azzizi_ My ultimate goal is to prepare .bench file from given TrustHUB benchmarks so that I will be able to prepare a graph (using .bench). From this graph, I will be able to extract features of a circuit such as Logic Gate Fan-in, Multiplexer input/output, loops in a circuit or any other information of circuit that can be included in a dataset.17:22
azzizi_I have also checked this :
tpbTitle: A problem in converting into bench format : yosys (at
azzizi_My question is what should be the proper sequence of commands to convert17:24
azzizi_benchmarks are verilog files btw17:26
ZipCPUazzizi_: Yosys doesn't have a write_bench command17:26
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ZipCPUazzizi_: To know the commands yosys supports, feel free to run "yosys" in its interactive mode and then issue the command "help"17:34
ZipCPUAll of the various write formats will show up at the end of the list.17:34
azzizi_So I can't use write_bench in Yosys but in ABC right ?17:37
ZipCPUThat sounds about right17:38
azzizi_So may I ask if you think I should include the 'techmap' and the 'dfflibmap -liberty mycells.lib' commands?17:39
ZipCPUI'm not much of an expert with the techmap commands, so I'd have to defer to someone else for that answer.17:40
azzizi_Thank you ..should I wait here ? I am curious because these two commands are only different to what Clifford suggested in the reddit link I had posted earlier17:41
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ZipCPULet's see if daveshah is around at all ....?17:42
awygleazzizi_: are you currently doing the techmapping and then the bench writeout is failing?17:43
awygleor are you currently *not* including the techmap commands17:43
azzizi_<Zipcpu> Also in the imgur it is written that the write_bench command is for ABC I think maybe17:44
azzizi_<awygle> Please check this :,    I am exactly using this sequence17:45
azzizi_Nothing is failing though...but I wonder if I am doing it correctly17:45
azzizi_because the .bench and .blif format that I am getting, do not have a regular pattern from which I can proceed further. In .bench files I am getting LUTs instead of gates. I gates in .bench and .blif files are incomprehensible17:46
awygleand you're expecting NAND's instead of LUTs.17:46
awygleyou need to pass your liberty file to your techmap command, i think17:47
awygleyou're only mapping FFs to your liberty file, not anything else, so everything else is yosys internal cells, which apparently are LUTs17:47
azzizi_May I bother you by asking what the proper sequence of commands should be17:48
awyglei think it should be as simple as replacing `techmap` with `techmap -map mycells.lib`. but i've never done anything like this, so this is educated guesswork.17:49
azzizi_Thanks very much for the response17:50
awyglehmm actually, if that doesn't work, try adding `abc -liberty mycells.lib` after the dfflibmap pass17:50
awygleand that is the extent of my ability (and desire) to guess at this. good luck!17:51
azzizi_Okay I will let you know the update17:51
azzizi_thanks again17:51
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