Tuesday, 2018-06-05

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mithroAnyone know why arachne is not using the global network for this clock signal?02:07
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tpbTitle: Snippet | IRCCloud (at www.irccloud.com)02:11
mithroMy understanding is that arachne should have chosen glb_netwk_4 as  io_tile 0  9  io_0 can be routed directly onto glb_netwk_4?02:13
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awyglei can't comment on whether that tile correctly maps to glb_netwk_4 in the part you're using, but i do know arachne's global promotion rules are fairly primitive02:24
awygleso it's possible it's just deciding not to promote02:24
mithroawygle: Any way to force it?02:48
awyglemithro: manually instantiate the primitive?02:48
awygleThere are examples of how to do that in icefuzz/tests/sb_gb.v and sb_gb_io.v02:49
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awygleI know how to force arachne *not* to promote but I don't think you can do the opposite except from verilog.02:50
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promachawygle: For temporal induction,  why https://i.imgur.com/yIQ2dTm.png does not follow assertion in line 277 ?03:26
promachjust for info, line 277 had passed BMC03:26
tpbTitle: UART/test_UART.v at development · promach/UART · GitHub (at github.com)03:26
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awyglelol hi promach03:33
awygleYou almost certainly want {cnt{1'b0}} for one thing03:34
promachI have already tried that03:34
awygleThen you're probably not asserting enough intermediate steps to pass induction03:35
awygleI don't have time right now to fully work through your logic though03:35
awygleTry running with some of the other proof engines and see if you get a proof there, maybe03:36
awygleLike abc pdr03:37
promachawygle: ok03:39
mithro.attr loc "0,9/2"03:49
mithroawygle: That seems to me like it decided to use User->Global routing rather than using the IO->Global routing...03:52
awyglemithro: yeah, looks like03:52
awygledid you instantiate it manually?03:53
mithroawygle: No - looking at the code - it looks like it always promotes in this way....03:53
awyglehuh, weird03:53
awygleI sort of remember there being something weird about the IO global routing but you need daveshah to tell you more03:54
awygleAlso possible that cseed just didn't bother with the other kind03:54
mithroawygle: https://github.com/cseed/arachne-pnr/blob/master/src/global.cc#L482-L52203:55
tpbTitle: arachne-pnr/global.cc at master · cseed/arachne-pnr · GitHub (at github.com)03:55
mithroawygle: Were as I want this -> https://github.com/cseed/arachne-pnr/blob/52e69ed207342710080d85c7c639480e74a021d7/tests/simple/sb_gb_io.blif#L34-L3504:02
tpbTitle: arachne-pnr/sb_gb_io.blif at 52e69ed207342710080d85c7c639480e74a021d7 · cseed/arachne-pnr · GitHub (at github.com)04:02
awygleoh yeah daveshah actually mentioned that in openfpga awhile back04:02
awyglethat looks reasonable yeah04:03
awyglehttps://irclog.whitequark.org/~h~openfpga/2018-05-09#22045733 this page of logs has the bulk of the discussion I had with daveshah about globals, and some discussion of arachne's behavior between daveshah and whitequark04:10
tpbTitle: ##openfpga on 2018-05-09 — irc logs at whitequark.org (at irclog.whitequark.org)04:10
mithroI don't quite get this example -> https://github.com/cseed/arachne-pnr/blob/52e69ed207342710080d85c7c639480e74a021d7/tests/simple/sb_gb_io.v04:12
tpbTitle: arachne-pnr/sb_gb_io.v at 52e69ed207342710080d85c7c639480e74a021d7 · cseed/arachne-pnr · GitHub (at github.com)04:12
mithroShouldn't there be a "wire clk;" in there?04:13
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)04:16
mithroThat seems to do what I want...04:16
awygledefault_nettype strikes again04:16
awygleimplicit wires are entirely legal04:17
mithroAnyone know how to solve "ERROR: Failed to import cell $techmap\gate.$procdff$7 (type $dff) to SAT database." ?04:23
mithroIt seems like global nets are now being output by vpr correctly.....04:24
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mithroawygle: any idea?04:26
mithrodaveshah: I'm assuming you haven't gotten up yet...04:26
awyglemithro: huh. No clue. Looks like a problem with your equivalence check and not necessarily the circuit tho.04:41
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mithroawygle: Makes it hard to check though :-P04:47
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keesjalright . I was done waiting for the tinyFPGA and ordered a icestick11:28
keesjthis is the 4th ice board I ordered but will be the first one I have in my hands11:30
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mattvennI have a question about dynamic circular left shift16:37
mattvennI'm having a go at implementing an FFT in verilog16:37
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mattvennI'm following along with this paper  git remote add origin [email protected]:mattvenn/fpga-fft.git16:38
mattvennand for the ordering of the butterfly pairs, we can get the order by a left shift of the level and index of the butterfly16:39
mattvennit's something that I would have thought would be easy to do in hardware16:39
mattvennbut what I've ended up with is concatenating the register twice so as I shift it I don't lose bits16:39
mattvenngit remote add origin [email protected]:mattvenn/fpga-fft.git16:40
mattvenndang! This link: https://github.com/mattvenn/fpga-fft/blob/7c90dddd19a9fd072872658dbe8b31f06fe2a2da/hdl/agu.v#L4416:40
tpbTitle: fpga-fft/agu.v at 7c90dddd19a9fd072872658dbe8b31f06fe2a2da · mattvenn/fpga-fft · GitHub (at github.com)16:40
mattvennwhich seems a waste of flops16:40
mattvennany suggestions on how to improve this?16:40
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mattvennI've just seen a paper on the sliding DFT17:37
mattvennlooks much simpler, why would I use a DFT over a sliding DFT?17:38
mattvennas in the Cooley-Tukey implementation17:38
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ZipCPUAs I recalled, I didn't have much struggle doing the bit reverse in my own pipelined FFT implementation18:06
ZipCPUAre you doing this in a pipelined or block fashion?18:06
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knielsena dynamic bit shift is often called a "barrel shifter" - it does take some extra logic over a fixed shifter18:30
ZipCPUYeah, but ... a bit reverser doesn't require a shifter at all18:31
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knielsenthat's probably true :-)18:32
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mithroDoes anyone here know how to read the output of a failed equivalence check from yosys?20:26
mithroThe output I have is https://paste.ubuntu.com/p/dgzVfk4Wpc/20:28
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)20:28
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mithroZipCPU: any idea?20:37
* ZipCPU is taking a peek20:37
mithrodaveshah: ^20:38
daveshahHave a look at the cmp signals20:38
* ZipCPU has yet to (successfully) try out the equivalence checking capability of yosys20:38
daveshahIf they are low, there is a mismatch20:38
daveshahThere might be a way to get a vcd file, but I'm not sure20:40
daveshahThe other option is just to simulate the two for 1000 cycles20:40
daveshahmithro: try adding -dump_vcd <file.vcd> to the sat command20:41
daveshahThen you'll get an easier to observe counterexample trace20:42
mithro   518 \cmp_LED2                    0         0             020:43
mithro   518 \gate_LED2                   0         0             020:44
mithro   518 \gold_LED2                   1         1             120:44
daveshahThat's clearly the first mismatched20:44
daveshahThe vcd file will be clearer20:44
mithrodaveshah: Well I think 514 is?20:44
daveshahYeah it is actually20:46
mithrodaveshah: Okay -- I have the vcd file20:50
daveshahWhat's it looking like in gtkwave?20:52
mithrodaveshah: http://hopper.mithis.com/~tim/out.vcd20:52
daveshahNot at computer now20:52
mithrodaveshah: It seems to go wrong when "trigger" goes high....20:54
daveshahmithro: I think that's a SAT solver output indicating that it's gone wrong20:54
daveshahCan you post a screenshot where it goes wrong?20:54
daveshahLooks like LED2 is broken21:00
daveshahmithro: can you post the HLC and the bitstream Verilog?21:00
mithrodaveshah: https://paste.ubuntu.com/p/nZQPRSHXqr/ HLC21:01
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)21:01
mithrodaveshah: https://paste.ubuntu.com/p/HNf2wvT8TS/ generated verilog21:04
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)21:04
mithrodaveshah: Can icebox_vlog use the .sym stuff?21:04
daveshahmithro: yes21:04
daveshahAlthough it gets tacked on at the bottom21:05
mithrodaveshah: IE Is there a way to get the verilog output to be nicer....21:05
daveshahAs a bunch of assigns21:05
mithroLooks like icebox_vlog has "-L lookup symbol names (using .sym statements in input)"21:07
daveshahI can't immediately see what is wrong tbh21:08
daveshahPersonally I'd simulate the icebox_vlog output to make sure it's not an equiv check issue first21:09
mithrodaveshah: Any idea if the .sym can go through HLC21:09
daveshahNot sure21:09
mithroGuess I'll just generate a separate .sym file and cat it onto the end of the asc file...21:13
mithrodaveshah: I'd actually like to do some more LUT tests to make sure the LUT init is okay....21:14
daveshahmithro: I'd say that's the most likely issue21:14
daveshahThe routing looks OK at a glance21:15
daveshahMaybe VPR is swapping LUT pins or something weird?21:15
daveshahIt's clearly almost right...21:15
daveshah3 bits work fine21:15
mithrodaveshah: I also wonder if something around resets?21:15
mithrodaveshah: But I can't see anything around resets in the verilog?21:16
daveshahmithro: No, I don't think so21:16
daveshahThat all looks fine21:16
daveshahBut definitely run it through a simulator so you can see all the internal signals21:16
mithrodaveshah: now I need to figure out how to do that :-P21:21
daveshahmithro: it would be a nice makefile target to have21:22
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mithrodaveshah: Agreed21:24
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daveshahmithro: https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/Makefile#L22-L2621:26
tpbTitle: icestorm/Makefile at master · cliffordwolf/icestorm · GitHub (at github.com)21:26
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mithrodaveshah: Guess I could try and pnr these demos....21:44
daveshahmithro: yeah, give it a go21:44
mithroNow if only my icesticks would make it to me instead of going on a mail trip around multiple buildings....21:45
daveshahThese again take many clock cycles to do anything, so you'll have to either reduce the divider or run a long simulation21:45
mithrodaveshah: I should be able to just run the test bench, right?21:51
daveshahmithro: yes21:59
daveshahBut it might take a little while22:00
daveshahFor such a simple design should be fine though22:00
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