Monday, 2018-06-04

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promachZipCPU: are you referring specifically to line 277 in your previous statement ?02:15
ZipCPUYes I was.  Now that I look at it again ... does {cnt{0}} have cnt 0's in it?02:21
ZipCPUI've always used an extra set of parens, {(cnt){1'b0}} ... but I'm known for overusing the parentheses02:22
promachZipCPU: overusing the parentheses helps in this case, and I hope this fix is not "temporary"02:31
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mattvenndid people see this E glitching arduinos with lattice ice40?
tpbTitle: GitHub - deanjerkovich/avr-glitch-101: the most basic introduction to performing a Vcc glitch attack (at
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mattvennI've made a plugin to make your keyboard feel horrible09:24
tpbTitle: GitHub - Dygmalab/Kaleidoscope-AdjustableLatencyJitter (at
mattvennwoops wrong channel - sorry09:25
keesjyea a few people solved the rhme2 glitching challenges using an FPGA ( was also nice)09:28
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promach_ZipCPU: now with a different computer, using your overused parentheses does not work for induction15:37
ZipCPUTry updating your yosys install15:37
ZipCPU(on both computers)15:38
promach_just updated less than 24 hours ago15:38
promach_I can do it again now15:38
ZipCPUIf they are both up to date, I wouldn't expect any differences15:42
promach_just wait for a while, I am updating yosys to the git version15:43
promach_I mean the latest git15:43
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promach_ZipCPU: updated to latest git15:54
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promach_ZipCPU: I will update yosys on the other computer16:12
promach_but again, adding parentheses does not really help for induction16:12
ZipCPUIf it changes the meaning of the expression, then yes it helps.16:13
promach_I just hope that I could get around this induction bug before next month, hahaha16:15
promach_I hope god would grant my wish ;)16:16
promach_ZipCPU: just curious, did you actually run my coding under induction ?16:17
ZipCPUDid I invoice you?16:18
promach_oh sorry16:18
promach_wrong question, sorry16:18
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rohhi there20:14
daveshahroh: hi20:14
shaprgod afton20:14
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rohi am searching for somebody who could help me get my ice40 board flashed. i got the olimex board and the olimex-arduino for flashing via usb. i can read the flash-id fine, but writing the flash never seems to end20:16
azzizi_I am trying to convert verilog to bench file and the sequence of commands follow :20:16
azzizi_YOSYS: read_verilog filename.v :   In case of hierarchy:  read_verilog filename1.v read_verilog filename2.v . read_verilog filenameN.v  hierarchy -check -top filename_of_topmodule // (Don't put the extension of .v) techmap                                                           // Mapping to internal library. dfflibmap -liberty mycells.lib                             //Technology mapping for flipflops.  write_blif filename.blif  A20:16
rohiceprogduino just continues with .....20:16
azzizi_oh no20:16
rohif this is out of scope, i'm sorry and will search elsewhere20:17
azzizi_anybody can help me to convert from verilog to bench please20:17
daveshahroh: not sure how many people here use the olimex boards20:17
daveshahazzizi_: have you seen
tpbTitle: CliffordVienna comments on A problem in converting into bench format (at
rohi understand. i just bought it because it was basically the same price and had some ram chip on it which i liked. could come in handy20:18
daveshahroh: yeah they're really nice board. just don't have any experience with them20:19
azzizi_yes I saw it20:19
azzizi_so does it mean the problem remains ?20:19
daveshahroh: could it be a signal integrity issue maybe, why the flashing fails?20:19
rohdaveshah: i dont think so. it detects the flash type fine.. and since its only spi over 10cm flatflex from some avr20:20
daveshahazzizi_: as clifford posts, I don't think there is necessarily a problem.20:20
daveshahazzizi_: what is it doing wrong?20:20
daveshahroh: I'm afraid I can't really think of anything else. It is probably worth contacting Olimex directly.20:21
rohwell.. thanks anyway :)20:21
azzizi_In .bench files I am getting LUTs instead of gates20:22
azzizi_just like that guy20:22
ZipCPUWhat are you using to do your synthesis or tech mapping?20:23
* ZipCPU reads the backlog and finds out20:23
azzizi_techmap                                                           // Mapping to internal library. dfflibmap -liberty mycells.lib                             //Technology mapping for flipflops.20:23
azzizi_dfflibmap -liberty mycells.lib20:24
ZipCPUDoes yosys properly map to the cells in your mycells.lib?20:24
azzizi_write_blif filename.blif20:24
azzizi_how do I understand if it doesn't ? actually it's a problem my friend is facing20:25
ZipCPUBoth mycells.lib and filename.blif should be textual and (somewhat) legible20:26
ZipCPUIf yosys does its job correctly, it should map the design into the cells in the mycells.lib library20:26
rohyay. i think i fixed it.20:43
rohit seems if you want to run the olimex board from the uisp-3.3v one needs to solder a jumper on the bottom20:44
rohby feeding it peripheral (no jumper, only via the iopins and the clamping diodes) one can exec one spi-flash instruction, the second one fails20:44
daveshahroh: oh nasty, glad you fixed it!21:00
rohnow i can finally start hacking on it :)21:04
rohwow.. my yosys is nearly 160mbyte? is that normal?21:12
rohah. debug symbols.21:14
shaprstrip it!21:15
ZipCPUNot sure I've ever seen a milli-byte before.21:16
shapris that a mibibyte?21:17
rohits a me-too-lazy-for-shift byte21:18
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