Wednesday, 2018-05-30

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shapris there some way to donate money to yosys development?00:42
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ZipCPUshapr: Wrong time of day to ask.  Most of the team is on European time.00:43
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qu1j0t3scrollback is 24 hr though00:46
* ZipCPU is trying to write an article about formally verifying a clock switch--quite the fascinating topic00:57
sorearA clock switch?01:03
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ZipCPUIt's not so much an FPGA design as an ASIC one, but it makes a nice and simple example to illustrate how formal properties can be used to describe two clocks.01:17
ZipCPUI found the code and example via google.  Formally verifying it yielded a "let the buyer beware" sort of moment which should make the article more amusing.01:18
sorearSo a circuit that switches at runtime between two or more clock sources?01:18
ZipCPUAnd the trick is ... the circuit can't be allowed to glitch.  The two switch needs to produce a glitch free result that maintains timing properties no worse than the fastest clock.01:21
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sorearDo you allow it to be worse than the slowest clock?02:15
sorear(For circuits requiring a minimum frequency)02:15
ZipCPUHeheh ... while swapping clocks, the "down" period may be longer than the down period of the slowest clock, so yes.02:17
ZipCPUSee ... part of the story of this article is what I discovered while trying to formally verify the clock.02:17
ZipCPUI found the clock switch design on line, and so I'm just formally verifying it.02:18
ZipCPUThe original design can be found on EETimes, in an article written by Mahmud02:18
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tpbTitle: Yosys Open SYnthesis Suite :: Donate (at
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azzizianyone can tell me how do i see all previous chats17:32
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shaprazzizi: I don't know if yosys is logged17:37
shaprazzizi: oh wait, check the channel topic17:37
tpbTitle: #yosys on 2018-05-30 — irc logs at (at
azziziThanks very much17:41
azzizi00:02 <ZipCPU> Hi, azzizi! This is a place you can hold a conversation--so you can do more here than just ask questions.  00:03 <ZipCPU> I know the various "synth" steps are usually composed of many separate steps within a design, and these separate steps can be selected and activated individually.  00:04 <ZipCPU> From that standpoint, it sounds like inputting a design via read_verilog, followed by some amount of processing, followed17:45
azzizisorry about that17:45
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azziziMy apologies ; this follow up questions are in reference to 2018-05-24. In coversation with : <ZipCPU> <daveshah> <awygle>18:08
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azzizi1. From what I understand AST forms are for debugging only and can't be made changes to...I just want an intermediate format, be it anything for yosys (awygle suggests ILANG) that doesn't lose any source code information.18:10
azziziCont..1. So I could make a custom Yosys pass ...make some changes to ILANG to get a legal file and ues write_verilog to get a modified format of the output?18:12
daveshahazzizi: Yes, ILANG is definitely the intermediate format you will want to use18:16
azzizi2. Also, according to <daveshah> the write_verilog dumps the internal RTLIL to verilog. For a source code, I had read in using read_verilog and dumped using write_verilog; now using the design compiler software(for tsmc 25nm) I synthesized and it worked! So the RTLIL format is itself synthesizable?18:16
daveshahazzizi: Yes, RTLIL is synthesisable. I don't think it even supports any if many simulator-only constructs18:16
daveshahIf you write a Yosys pass, you work on the RTLIL structures directly rather than the ILANG representation of it, BTW18:17
azzizi3. The intermediate RTLIL can be synthesized to ASIC and FPGA both ? without losing any information ?18:17
azzizi4. <daveshah> Can you please tell me some examples of what information read_verilog looses if possible?  thanks much......18:18
daveshahazzizi: pre-synthesis RTL can be synthesised to ASIC or FPGA. Obviously information, but not functionality, is lost during synthesis as optimisations and technology mapping will occur18:23
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daveshahread_verilog will lose things like comments and the precise structure of the code, AFAIK18:23
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azzizi<daveshah> Is the output (synth.v) from the command write_verilog synth.v is the pre-synthesis RTL?18:38
azziziAlso, could you please elaborate on the comment " I don't think it even supports any if many simulator-only constructs"18:39
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daveshahazzizi: the output is simply the current design in Yosys18:42
daveshahit will be pre-synthesis until you run synthesis commands (i.e. synth)18:42
daveshahfor simulator only constructs, I mean things you would use to create stimulus (delays for example), etc18:43
azziziso if I use read_verilog and immediately then I use write_verilog file.v .............the file.v is the presynthesis verilog RTLIL format from which I can either way ASIC or FPGA18:49
azziziI can go *18:50
azziziright <daveshah> ?18:53
daveshahazzizi: yes, that is correct18:54
azzizithaks very much....much obliged18:54
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