Monday, 2018-05-28

*** tpb has joined #yosys00:00
ZipCPUSo ... does the SAT induction solver work from the (potential) assertion error timestep backwards, or from a generic timestep forwards?00:04
*** promach has joined #yosys01:13
*** dxld has quit IRC01:51
*** dxld has joined #yosys01:51
*** leviathan has joined #yosys03:05
*** Guest82714 is now known as jayaura03:59
*** pie__ has quit IRC04:16
*** pie_ has joined #yosys04:16
*** leviathan has quit IRC04:19
*** leviathan has joined #yosys04:20
*** leviathan has quit IRC04:22
*** leviathan has joined #yosys04:23
*** promach has quit IRC05:23
*** emeb_mac has quit IRC06:53
*** dys has quit IRC06:53
*** dys has joined #yosys06:55
*** dys has quit IRC07:21
*** AlexDani` has joined #yosys07:40
*** proteus-guy has quit IRC07:40
*** AlexDaniel has quit IRC07:42
*** proteus-guy has joined #yosys08:00
*** promach has joined #yosys08:50
*** dmin7 has joined #yosys08:56
*** Kooda has quit IRC09:34
*** Kooda has joined #yosys09:35
*** quigonjinn has joined #yosys09:36
*** proteus-guy has quit IRC09:45
*** promach has quit IRC09:56
*** ovf has quit IRC09:57
*** ovf_ has joined #yosys09:59
*** marbler has quit IRC10:05
*** andi- has quit IRC10:05
*** maartenBE has quit IRC10:07
*** maartenBE has joined #yosys10:10
*** andi- has joined #yosys10:13
*** marbler has joined #yosys10:15
*** X-Scale has quit IRC10:37
*** X-Scale has joined #yosys10:43
*** proteus-guy has joined #yosys10:44
dmin7ZipCPU: i tried to simplify the read and write to the 2d array (triggers) .. in the simulation it runs fine, but it still gets synthesized as FFs and not BRAM .. any idea?12:00
tpbTitle: [VeriLog] module icosoc_mod_triggerrec #( parameter integer CLOCK_FREQ_HZ = 0, // unused - (at
* ZipCPU takes a peek12:01
dmin7that was fast (:12:01
ZipCPUI think you'll still want to split the always block with if (triggers_*) up into two blocks.12:02
* dmin7 go try12:02
ZipCPUYou mentioned a 2D array.  I don't see any 2D arrays.  I see a 1D array of 32-bit words.  Is this what you meant by a 2D array?12:03
*** mirage335 has quit IRC12:03
dmin7oh, yes .. just array* sorry12:05
dmin7splitting it up doesn't change anything12:05
*** leviathan has quit IRC12:09
*** m_t has joined #yosys12:15
dmin7you also told me to not use the for loop for initialization12:17
dmin7without it it uses BRAM :o12:18
*** mirage335 has joined #yosys12:18
*** eduardo_ has joined #yosys12:43
*** develonepi3 has joined #yosys12:46
*** eduardo__ has quit IRC12:47
*** promach has joined #yosys13:50
*** emeb has joined #yosys14:23
ZipCPUSo, after formally verifying the CPU, the extra logic I added to pass grew the CPU by about 5% LUTs.  :/14:47
emebThe perfect circuit is like the speed of light - you have to add exponentially more resources to get asymptotically close to the goal.14:52
ZipCPUThe good news, I guess, is that I've just corrected a whole bunch of otherwise deadly hidden bugs within the CPU15:00
*** jwhitmore has joined #yosys15:39
*** dxld has quit IRC15:44
*** dxld has joined #yosys15:46
*** jonsmith has joined #yosys15:46
*** FabM has quit IRC15:47
*** jwhitmore has quit IRC15:56
*** jwhitmore has joined #yosys16:13
*** jwhitmore has quit IRC16:21
*** jwhitmore has joined #yosys16:23
*** develonepi3 has quit IRC16:29
*** leviathan has joined #yosys17:02
*** AlexDani` is now known as AlexDaniel17:06
*** jwhitmore has quit IRC17:11
*** promach has quit IRC17:12
*** dxld has quit IRC17:16
*** dxld has joined #yosys17:16
*** jwhitmore has joined #yosys18:14
*** dys has joined #yosys18:20
*** jwhitmore has quit IRC18:32
*** jonsmith has quit IRC18:41
*** jwhitmore has joined #yosys19:28
*** leviathan has quit IRC19:54
*** quigonjinn has quit IRC19:55
*** zkrx has quit IRC20:15
*** zkrx_ has joined #yosys20:16
*** m_t has quit IRC20:27
*** xerpi has joined #yosys20:38
*** sklv has quit IRC20:43
*** sklv has joined #yosys20:44
*** dxld has quit IRC21:03
*** dxld has joined #yosys21:04
*** gnufan has quit IRC21:21
*** gnufan has joined #yosys21:24
*** dmin7 has quit IRC21:28
*** gnufan has quit IRC21:31
*** dmin7 has joined #yosys21:33
*** dmin7 has quit IRC21:37
*** dmin7 has joined #yosys21:40
*** xerpi has quit IRC22:21
*** gnufan has joined #yosys22:29
*** jwhitmore has quit IRC22:35
*** gnufan has quit IRC22:46
*** gnufan has joined #yosys23:14
*** gnufan has quit IRC23:28
*** gnufan has joined #yosys23:31
*** gnufan has quit IRC23:39
*** ralu has quit IRC23:40
*** ralu has joined #yosys23:40
*** gnufan has joined #yosys23:42
*** emeb has quit IRC23:46

Generated by 2.13.1 by Marius Gedminas - find it at!