Thursday, 2018-05-24

*** tpb has joined #yosys00:00
*** digshadow has joined #yosys00:01
ZipCPUHi, azzizi!  This is a place you can hold a conversation--so you can do more here than just ask questions.00:06
ZipCPUI know the various "synth" steps are usually composed of many separate steps within a design, and these separate steps can be selected and activated individually.00:07
ZipCPUFrom that standpoint, it sounds like inputting a design via read_verilog, followed by some amount of processing, followed by write_verilog, followed by your processing, followed by read_verilog and the processing chain again, followed by write_whatever might suit your needs.00:08
ZipCPUBut ... getting back the original behavioral code from the platform specific Verilog code?  That sounds like a hard problem.00:10
*** emeb has quit IRC01:00
awygleILANG is a textual representation of RTLIL so it should not lose information. You should be able to modify the ILANG as long as you end up with a legal file. You might also consider writing a custom Yosys pass.01:03
awygleazzizi: ^01:03
*** emeb_mac has joined #yosys01:04
*** m_w has quit IRC01:08
*** digshadow has quit IRC01:09
*** digshadow has joined #yosys01:16
*** quigonjinn has joined #yosys01:24
*** digshadow has quit IRC04:00
*** digshadow has joined #yosys04:19
*** leviathan has joined #yosys04:43
*** seldridge0 has quit IRC05:02
*** quigonjinn has quit IRC05:03
*** dys has quit IRC05:48
*** proteusguy has quit IRC06:44
*** dys has joined #yosys06:54
*** emeb_mac has quit IRC07:16
*** dys has quit IRC07:24
*** quigonjinn has joined #yosys07:27
daveshahazzizi: neither write_verilog nor read_verilog perform any synthesis07:55
daveshahread_verilog reads in the source code and compiles it to a high level (architecture agnostic) RTLIL netlist07:55
daveshahwrite_verilog simply dumps the current internal RTLIL to verilog07:56
daveshahIf you want the output to be synthesised to a particular architecture, you need to call one of the synth commands, or manually set up your own sequence of commands to do synthesis, between read_verilog and write_verilog07:56
*** GuzTech has joined #yosys07:57
daveshahEven the first compilation step after read_verilog does loose some information, so you can't go back to the original input verilog07:57
daveshahSynthesis will cause much more significant differences though. The resulting verilog will still be functionally equivalent though.07:58
*** dmin7 has joined #yosys07:58
daveshahThe AST outputs are for debugging only, they are not a useful intermediate format as Yosys has no facility to read them in07:59
daveshahThe most useful intermediate format is ILANG08:00
*** ZipCPU has quit IRC08:00
*** ZipCPU has joined #yosys08:05
*** jwhitmore has quit IRC08:29
*** promach_ has joined #yosys08:45
*** digshadow has quit IRC08:46
*** digshadow has joined #yosys08:51
*** jwhitmore has joined #yosys09:04
*** grummel has quit IRC09:12
*** esden has quit IRC09:12
*** azzizi has quit IRC09:18
*** grummel has joined #yosys09:21
*** proteusguy has joined #yosys09:22
*** proteus-guy has quit IRC09:25
*** _whitelogger has quit IRC09:43
*** _whitelogger has joined #yosys09:45
*** FabM has joined #yosys10:01
*** maartenBE has quit IRC11:28
*** maartenBE has joined #yosys11:34
*** proteus-guy has joined #yosys11:49
*** develonepi3 has joined #yosys11:55
*** seldridge0 has joined #yosys12:07
*** maartenBE has quit IRC12:17
*** maartenBE has joined #yosys12:18
*** jwhitmore has quit IRC12:39
*** eduardo_ has joined #yosys12:43
*** eduardo__ has quit IRC12:47
*** seldridge0 has quit IRC13:05
*** seldridge0 has joined #yosys13:41
*** leviathan has quit IRC13:44
*** leviathan has joined #yosys13:47
*** emeb has joined #yosys13:51
*** cemerick_ has quit IRC13:56
*** [X-Scale] has joined #yosys14:21
*** X-Scale has quit IRC14:22
*** [X-Scale] is now known as X-Scale14:22
*** [X-Scale] has joined #yosys14:26
*** X-Scale has quit IRC14:28
*** [X-Scale] is now known as X-Scale14:28
*** promach__ has joined #yosys14:57
*** promach__ is now known as promach215:00
*** quigonjinn has quit IRC15:06
*** GuzTech has quit IRC15:10
*** cemerick_ has joined #yosys16:07
*** cemerick_ has quit IRC16:12
*** promach2 has quit IRC16:31
*** seldridge0 has quit IRC17:34
*** digshadow has quit IRC17:57
*** dys has joined #yosys17:59
*** leviathan has quit IRC18:05
*** dxld_ has joined #yosys18:13
*** dxld has quit IRC18:14
*** dxld_ is now known as dxld18:14
*** jwhitmore has joined #yosys18:33
*** seldridge0 has joined #yosys18:54
*** josh- has joined #yosys19:09
*** kehribar has joined #yosys19:15
*** awygle is now known as aygle19:16
*** aygle is now known as awygle19:20
*** guan has quit IRC19:28
*** guan has joined #yosys19:28
*** mlen has quit IRC19:29
*** mlen has joined #yosys19:31
*** cyrozap is now known as Guest193619:38
*** Kitlith is now known as Guest5094919:38
*** shapr is now known as Guest6377019:38
*** Guest63770 is now known as shapr19:38
*** josh- has quit IRC19:43
*** kerel has quit IRC19:48
*** cemerick_ has joined #yosys20:06
*** cemerick has joined #yosys20:10
*** mlen has quit IRC20:13
*** cemerick_ has quit IRC20:13
*** mlen has joined #yosys20:15
*** kerel has joined #yosys20:17
*** guan has quit IRC20:23
*** guan has joined #yosys20:23
*** dmin7 has left #yosys20:31
*** AlexDaniel has quit IRC21:09
*** AlexDaniel has joined #yosys21:09
*** jwhitmore has quit IRC21:12
*** azzizi has joined #yosys21:43
*** cemerick has quit IRC21:53
*** dxld has quit IRC22:01
*** digshadow has joined #yosys22:03
*** kehribar has quit IRC22:23
*** seldridge0 has quit IRC23:01
*** promach__ has joined #yosys23:11
*** promach__ is now known as promach223:18

Generated by 2.13.1 by Marius Gedminas - find it at!