Wednesday, 2018-05-23

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emeb_macZipCPU: Nice blog on filters01:28
emeb_macI've designed so many DSP pipelines that this kind of stuff is 2nd nature, but that doesn't mean it can't have rough spots.01:29
emeb_macJust wrapped up HDL design work on a big OFDM receiver - there were some "fun" bits in that. A frequency domain equalizer with all kinds of memory and feedback that took me nearly a month to get working...01:30
awygledang, that's impressive. ofdm is scary01:31
ZipCPU... Still working on my FFT here ...01:31
emeb_macOh fun!01:31
ZipCPUOnce the FFT is done, the rest of any OFDM design should be fairly easy in comparison.01:31
emeb_macWe just plopped down IP cores from the FPGA vendor.01:31
awyglei did a DSSS receiver once and the hardest part was locking to the code01:32
ZipCPUawygle: Yep!  Now, knowing what I do, I could probably do a DSSS receiver a lot cheaper than the last one I did ...01:32
emeb_macNot really much point in putting effort into the FFT when the vendor core is free and well optimized & debugged.01:32
awygleZipCPU: if i ever get back into the satellite radio market, i'll give you a call ;)01:33
ZipCPUemeb_mac: To each their own calling.01:33
awyglei have like 75% of a design for a quarter-watt couple-MHz SDR board for cubesats01:33
emeb_macZipCPU: if you're having fun :)01:33
awyglebut my business fell apart before i had reason to pull the trigger on it01:33
emeb_macZipCPU: and FWIW - there's a lot more to a successful OFDM system than just the FFT.01:34
ZipCPUemeb_mac: There's more to it than just that.  I keep seeing students trying to figure out why the proprietary vendor design isn't doing what they are expecting.  A nice clear open source design would therefore be valuable for understanding what's going on under the hood.01:34
ZipCPUemeb_mac: Well said, well said.01:34
emeb_macand yeah - having access to source is a good thing01:35
emeb_macOn a previous project we had the option of building or buying an LDPC decoder and decided to build it in house.01:35
ZipCPUI mean .... even if the design component works, sometimes it helps to trace through it to understand why your wrapper isn't working.01:35
emeb_macIt was hard but we learned a lot.01:35
ZipCPUOooohh ... LDPC, that's a fun one.01:35
awygleLDPC is super cool01:36
awygleanother good satellite tech01:36
emeb_macIt took a while but actually was cheaper than buying.01:36
ZipCPUThe last FEC decoder I built in Verilog was a product code, quite a fun challenge.01:36
emeb_macbecause the folks selling them want arm + leg.01:36
ZipCPUWell, if it works, it might just be worth both arms and legs ... just to spare you the hassle of finding the bugs in your own.01:37
emeb_macOTOH, for this project we needed a rate 1/2 Viterbi decoder and didn't want to waste effort on that so we just bought the Xilinx core.01:37
sorearIt would be nice if you could assume commercial IP was bug-free01:38
ZipCPUHeheh ... I remember building a 1/2 rate Viterbi decoder--wasn't in Verilog though.  C++ instead.01:38
ZipCPUsorear: Don't steal my innocence, please.  :D01:38
emeb_macThere's a lot of open source code for that stuff.01:38
emeb_macWe had a project that needed a BCH decoder and found one written in Verilog.01:39
emeb_macConverted it to our own favorite VHDL and it worked fine.01:39
awyglei wrote a BCH encoder in C recently01:39
awygleit really annoys me when FEC people don't pubish test vectors01:39
ZipCPUAw, come on ... it's just a linear system.01:40
awyglelike "i'm TRYING to be compatible to your stupid standard, throw me a bone here!"01:40
ZipCPUPick your favorite basis set and go.  That should be sufficient.01:40
awygleCRCs are the worst this way, historically lol01:40
tpbTitle: GitHub - russdill/bch_verilog: Verilog based BCH encoder/decoder (at
ZipCPUYeah, okay, I'll grant you CRC's.  There are just too many implementations of them.  Do they start with the zero state or the ones state, do you xor the result with zeros or ones when done, which way do the bits go in, etc.01:41
emeb_macI know Russ from elsewhere on IRC and actually sent him some bugfixes we found while using his stuff.01:41
ZipCPUI've wanted to blog about how formal can help doing CRC's for ethernet, but ... haven't gotten that far.  Really makes building them easy.01:41
emeb_macI'll bet01:41
emeb_macCRCs are interesting - we're using some in the OFDM project01:42
ZipCPUHeh ... it's even easier when you control the whole link.01:42
emeb_macyes, very.01:42
emeb_macmatch up the tx & rx. done.01:42
emeb_macbut then we model *everything* in Matlab before starting to code HDL01:43
emeb_macso we know what's going to happen up front.01:43
ZipCPUWell,  why not?  It's often faster and easier to do so.01:43
ZipCPUWhat I don't get are the newbies that try to build something really complex without first understanding the technology.01:43
emeb_macand since we don't grok formal, all our testing is vector-based with references from the Matlab sim01:44
ZipCPUThey then get confused as to why it doesn't work.  You ask about their pre RTL simulation, and just get blank looks.01:44
emeb_macyes - we see that too01:44
ZipCPUFormally verifying an FIR filter was a fun challenge.  Not your typical formal proof.01:44
emeb_macso many of our customers just start out throwing HDL at the wall01:44
emeb_macno verification process at all01:45
emeb_mac"we can debug on the bench - FPGAs make it easy!"01:45
emeb_macWhen an edit/compile/test cycle takes 2 hours, you can't get much debugging done in a workday.01:45
emeb_macI use Matlab to generate stimulus / response (with fixed-point implementation code) for the entire datapath.01:47
emeb_macthen we unit test each step in the path and end-to-end after integration01:47
ZipCPUYeah ... but you can do a *lot* of blogging during that time!01:47
emeb_macor watch cat videos!01:48
ZipCPUBeen there, done that, blogging increases my code quality, cat videos don't.01:48
awygleor play fetch with the cat01:48
ZipCPUFooseball anyone?01:48
awyglecat doesn't know how to play that yet01:49
ZipCPUThe other fun alternative here is to distract the security officer.01:50
emeb_macheh - work from home. no security officer.01:50
ZipCPUShe's works for a "Shepherd Security Services" firm.  It's a German company.01:50
emeb_macTacos al pastor Aleman01:51
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mattvennZipCPU: re: What I don't get are the newbies that try to build something really complex without first08:09
mattvennI think it's because when someone doesn't understand something, they don't understand how hard it will be08:09
mattvennso they are apt to choose projects well beyond their abilitites08:09
mattvennbut it's not necessarily a bad thing if they have patience and a lot of time08:09
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dmin7  route time 2089.26s13:11
ZipCPUdmin7: Which chip?  And ... how full was the design?13:37
dmin7pretty full x) LCs          6628 / 768013:55
dmin7i'm back to 160s now tho, all good13:56
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dmin7i do have a question though, if you have a moment14:08
tpbTitle: [VeriLog] module icosoc_mod_trigger #( parameter integer CLOCK_FREQ_HZ = 0, parameter - (at
dmin7seems like i am addressing the triggers (2d) array wrong14:09
dmin7(the for loop is just for some debugging data)14:10
dmin7ctrl_addr[3:0] should contain an id from 0-1514:10
dmin7and i have to split the bus read/write into two times 32bit .. but that works fine for the counter, so that shouldn't be the problem14:11
ZipCPUMost block RAM's cannot be initialized on reset.14:18
ZipCPU$readmemh usually works much better.14:19
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ZipCPULikewise, many design tools cannot recognize block RAM's buried deep into the logic of a process.  They require reads to be as simple as either an assignment or a, always @(posedge i_clk) trigger_data <= triggers[ctrl_addr[3:0];14:30
ZipCPUSometimes you can do your selection on the next clock, "assign ctrl_rdat = (ctrl_state == 0) ? trigger_data[63:32] : trigger_data[31:0];14:30
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shapry0 y0 y0 sys!17:04
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dmin7ZipCPU: thanks for the hint. (the problem was the memory addresses / index's i tried to use; 0-15 instead of multiples of 4)18:55
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azziziDo I post my question here ?21:00
azziziSo write_verilog transfers the intermediate RTLIL information of a source code to synthesizing according to the platform intended.  But suppose I wanted to see the RTLIL step for the code, capture it and edit some of it and then synthesize it, would it be possible with this tool?21:04
azziziI suppose I can see the RTLIL of any code with the dump_rtlil but can I make any changes to the generated RTLIL before the synthesize step?21:05
azzizi Also, which intermediate format: ast1 or ast2 or ILANG or RTLIL is the strongest i.e. doesn't lose any information? With that I mean all the source code indormation is there in that format?21:05
azziziAnd suppose I have a behavioral source code form where I get the platform-specific Verilog code using the write_verilog; my question is can I get back to the original behavioral code from the platform-specific Verilog code?21:05
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