Thursday, 2018-05-17

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shaprdoes yosys already have support for both Artix-7 chips in bunnies' NeTV2?
tpbTitle: NeTV2 | Crowd Supply (at
shaprI should just check the source19:25
shaprafter digging around in yosys/techlibs/xilinx/ , I still can't tell19:26
shaprbut I think it's all Xilinx 7-series? so yes?19:27
sorearshapr: define support19:27
shaprso, not full support?19:28
shaprI dunno19:28
daveshahyes, yosys has synthesis support for the artix-719:28
daveshahthere is no PnR yet19:28
daveshahbut the bitstream format is documented in project X-ray19:28
shaproh, I see19:30
awygledaveshah: there's no synth for the ecp5 yet, right?19:32
daveshahawygle: no, not yet19:32
shaprsilly question, what's the percentage cost for each step in FPGA design? where would optimizations pay off the most?19:32
daveshahobviously on my todo list19:32
awygleshapr: cost in terms of time? place+route, no question19:32
shaprah, that's good to know19:32
daveshahawygle: feel free to take it on if you want19:33
shaprcause that's the part I want to work on anyway19:33
awyglewell... "debugging". but that's slow because PnR is slow19:33
daveshahshapr: it's probably what needs work too19:33
awygleshapr: have you seen my list of papers on parallilizing it?19:33
awygle... imagine i spelled that right19:33
shapryeah, I'm trying not to dive too deeply into that list yet19:33
shaprcause I also have a day job19:33
shaprI really do not like simulated annealing19:33
awygledaveshah: i may just do that! have to see how other things work out.19:34
shaprfor this purpose, at least19:34
daveshahawygle: awesome19:34
awygledaveshah: speaking of trellis, what linux flavor are you running it on? i had issues getting your PoC running19:34
daveshahawygle: Arch Linux19:34
daveshahwith zsh19:34
daveshahPython 3.6.519:35
awyglehm. i was able to install diamond, but i had issues with building libtrellis and running the python bindings (solved the first, didn't solve the second)19:35
daveshahclang 6.019:35
shaprawygle: just to be clear, you mean this list?
tpbTitle: Place and Route Research · azonenberg/openfpga Wiki · GitHub (at
awygleon ubuntu something. 18.04?19:35
awygleshapr: yup19:35
shaprok, thanks19:35
daveshahboost 1.6619:35
awygleyeah i think boost::python was the problem19:36
awyglei'll probably just flip on an arch container, because lazy19:36
daveshahawygle: yeah, possibly easiest19:36
daveshahUbuntu looks like boost 1.65.1, so I can't imagine very different19:37
daveshahwhat error do you get?19:37
awyglei got a double free, iirc19:37
awygle(not sitting in front of it right now)19:37
awyglealso i had to downgrade CMake to 3.9 and change the boost::python entry to get libtrellis to build19:38
awygledowngrade the CMake version requirement, that is19:38
daveshahok, de-Arch-ification was on my todo list once I have the basics done this weekend19:38
daveshahthe double free is something else19:38
daveshahtry this branch:
tpbTitle: GitHub - daveshah1/prjtrellis at develop-fuzz (at
daveshahit was a problem in the devices.json file in fact19:39
awygleah, interesting19:39
daveshahawygle: The interconnect fuzzing framework is now in place, in the branch. After fixing one or two minor issues and speeding up with parallelisation, the logic tile should be completely fuzzed fairly soon, hopefully over the weekend.19:47
awygledaveshah: awesome!19:48
daveshahJust to give you an idea where things are at19:48
daveshahI've run it now for a few hours and it's a bit past halfway, but an optimisation I added causes it to miss the odd interconnect19:48
awygleso the next steps would be, perhaps independently, "fuzz other tiles" and "yosys support""?19:48
daveshahYes, exactly19:48
daveshahThe next tile steps are (i) interconnect tiles (CIBs) which are simply a case of reusing the logic tile fuzzer without the logic bits and (ii) IO tiles which are a project unto themselves19:49
daveshahwould you be interested in (ii) ?19:49
awygleit might be useful to put together a semi-prioritized list that people could indicate their targets on. i know there's at least two or three people interested in getting involved (including myself)19:49
awygleyeah, sure! sounds like fun :)19:49
daveshahThere's a crude todo list in the README19:50
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daveshahawygle: another job that needs doing, and could easily be done in parallel to fuzzing, is to document the timing model of the ecp521:00
daveshahPlenty to work on, that's for sure...21:01
awygletiming model sounds less like my thing tbh. less development, more attention to detail21:03
daveshahawygle: sure21:03
awyglefuzzers and yosys support are the things i have my eye on21:03
daveshahawygle: Yosys support is probably the most immediately rewarding, because it will also make Diamond better21:04
daveshahFuzzers are probably the most useful right now though21:04
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sorearAre power models a thing of interest?22:00
awygleI'd say so yes22:02
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