Thursday, 2018-05-10

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cr1901_modern I found this mystery yosys script (not commited). Corresponds to this repo:
cr1901_modernLast modified: Aug 25, 201602:10
tpbTitle: GitHub - cr1901/gp4-tests: A set of test Verilog sources for the GreenPAK 4 to exercise openfpga functionality. (at
cr1901_modernPretty sure I didn't start formal verification till May 2017?02:10
cr1901_modernA mystery indeed ._.02:10
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dmin7hmm .. so it seems like icosoc and also picosoc can't actually address the spi flash after initialization (on the icezero).11:12
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dmin7is there any icosoc / picosoc examples out there that have the spi flash directly attached to the ice40 and external pi/micro that i might have missed?11:14
dmin7i found the micropython port11:14
dmin7the black ice ii (icosoc) .. but that just removes all of the spi flash components11:15
dmin7tinyfpga .. but it doesn't seem like he pushed any changes to the picosoc fork11:15
dmin7and this, i guess:
tpbTitle: GitHub - grahamedgecombe/picosoc-uip: uIP 0.9 PicoSoC/PicoRV32 port (at
dmin7the micropython port would be interesting, but it gives me a "micropython.blif:10708: fatal error: unknown formal `CLKHFEN[0]'" after changing the chip and package name and .pcf assignments to the 4K11:19
daveshahdmin7: there is no internal oscillator in the 4k11:41
daveshahyou will have to modify it use an external clock input11:41
ZipCPUdaveshah: You've done a lot of work with the picosoc, right?  Have you ever tried to set up the flash to start immediately on power up?11:48
daveshahZipCPU: I've only ever used "plain" picosoc, which is always configured like that11:49
daveshahI've never used icosoc11:49
daveshahThe micropython example for example just boots straight from flash11:49
daveshahdmin7: a plain picosoc example that does this is in the base picorv32 repo:
tpbTitle: picorv32/picosoc at master · cliffordwolf/picorv32 · GitHub (at
daveshahyou'll just need to change the pin assignments for the icezero11:51
dmin7daveshah: i tried that, doesn't run either .. i have to double check things tho11:52
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daveshahdmin7: you might need to change the UART divider, if your clock is different?11:53
daveshahlooking at the icezero its clock is 100MHz11:53
daveshahso you'll need to reduce that, probably using a PLL11:54
daveshah12MHz is I think what that example is designed for11:54
dmin7a lit led would be fine for a start (:11:57
dmin7the picorv32 should run fine with the 100mhz clock tho?11:57
daveshahdmin7: 100MHz is probably a bit fast for picorv32 on iCE4011:58
daveshahyou'll have to see what icetime says when running your design through it11:59
dmin7it says: nope12:07
dmin7.. ok, i'll try to get picosoc running with lower clock then12:07
dmin7(maybe on the icoboard/icosoc the XO2 chip does do more than just passing thru the SPI signals 1:1?)12:10
daveshahdmin7: Yeah it might be you have to set an IO before the SPI signals get passed through12:11
daveshahI'm not sure12:11
dmin7hmm .. terminate called after throwing an instance of 'std::out_of_range'12:35
dmin7  what():  map::at12:35
dmin7make: *** [Makefile:24: hx8kdemo.asc] Aborted (core dumped) :S12:35
dmin7( )12:37
tpbTitle: [Bash] [picosoc]$ make hx8kprog yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo - - (at
daveshahdmin7: you can't use clk directly and through a PLL40_PAD at the same time12:39
daveshahit's a terrible error message I know12:40
daveshahyou can remove the reset counter, and just connect resetn to locked12:40
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mazzooplaying on picosoc; why can't I insert the PLL as main clock? icetime says 30MHz is possible, but even with 12MHz (==input xtal) the runtime stalls15:24
daveshahmazzoo: What board are you using?15:26
daveshahSeveral popular boards have broken VccPLL wiring15:26
mazzooaxelsys breakout board15:27
mazzoopll works fine for standalone a 135MHz VGA sig gen15:27
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mazzooupscaling from the 12M xtal15:30
daveshahmazzoo: should be OK then15:31
daveshahCan you post your complete design somewhere?15:31
daveshahDo you have resetn driven by pll locked?15:32
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mazzoodaveshah: oh, i ignore pll lock, but there's a resetn counter15:33
daveshahTry connecting resetn to locked15:33
daveshahThe clock output may otherwise be unstable for a bit and cause problems by corrupting state15:35
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mazzooworks perfect.15:45
mazzoothanks again!15:45
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daveshahmazzoo: awesome!15:50
develonepi3Hello Pin C8 is my USER_CLK comes from a 100MHz osc. It is connected to IOT_197_GBIN1 on HX8K.16:01
develonepi3When I try using it for as an input to PLL I get the fatal error: bad constraint on `i_clk': no PLL at pin C8.16:01
develonepi3Can only certain pins be used as inputs to PLL?16:04
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daveshahdevelonepi3: use the SB_PLL40_CORE instead of SB_PLL40_PAD variant (and REFERENCECLK in instead of PACKAGEPIN)16:07
develonepi3Thanks will check that out.16:10
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thoughtpoliceI have a bit of an odd question, perhaps. I'm basically just trying to get some cell numbers on a large design when mapped to an ASIC gate library (.lib) -- but one issue is that when I do synthesis, all of my RAMs in the original design are mapped to DFFs, which clearly skews the metric; in reality these would be SRAMs or whatever. Does anyone know of a good way to ignore memory->DFF conversion for some part of the hierarchy?18:31
daveshahthoughtpolice: its just a case of not running the "memory" pass on those parts to leave the memory as a black box I think18:44
daveshahBut I'm not sure of the details18:44
thoughtpoliceYeah, I just realized I stupidly had a 'memory' hanging out in my script. *facepalm*18:45
thoughtpoliceBut that does seem to be the right track and was my original thought; blackbox it somehow18:46
ravenexpis there any timeline for yosys 0.8 release?18:46
daveshahravenexp: I think I heard some time over the summer.18:47
ravenexpit seems like it went from 1/2 years between releases to 1 1/2 years18:48
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dmin7hmm, so i did some SPI debugging. seems picosoc starts to read the flash from offset 0 and then stops after about 130kB and then nothing happens ever thereafter ..20:17
tpbTitle: Unsee Free online private photos sharing (at
dmin7i also noticed that 'make spiflash_tb' fails with a lot of errors, but i guess that has nothing to do with it s)20:19
daveshahdmin7: I wouldn't worry about the testbench20:22
daveshahCan you post your top module now?20:22
tpbTitle: [VeriLog] /* * PicoSoC - A simple example SoC using PicoRV32 * * Copyright (C) 201 - (at
dmin7went down to 2mhz for testing20:25
daveshahdmin7: looks fine to me20:26
dmin7i do get a 2mhz clock and it looks quite stable on my DSO Quad mini x)20:26
daveshahCan you post a LA trace including CS please?20:27
dmin7LA trace?20:28
* dmin7 rather new to the whole of this :)20:28
daveshahLogic analyser trace - like before, but also with chip select20:30
dmin7oh, good question .. i don't have it in there because last time it wouldn't let me flash anymore when i connected the CS to the logic analyzer too20:32
dmin7which might be a hint that there is sth wrong with CS? x)20:32
* dmin7 go try again20:33
dmin7yip, does not like to be connected to the LA20:36
dmin7(the whole test setup is a bit of a mess atm because i had to connect everything with cables, but i guess if it works for the CLK etc it shouldn't be problem for CS either, already tried switching the gpio pin on the pi and using a different cable for CS)20:38
daveshahThat seems a bit weid20:40
daveshahIs this an icoboard or an icezero again?20:41
daveshahSo no MachXO involved then20:42
dmin7it works when i put 460ohm resistor before the LA :o20:43
daveshahJust thinking, reading 130kB from flash 0x0 sounds suspiciously like the fpga loading its bitstream20:43
daveshahOh interesting20:43
dmin7shouldn't those inputs be high impedance?20:43
dmin7with working i mean i can make a trace, not that it runs (:20:44
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daveshahYes, they should be20:45
daveshahIt might be the LA's capacitance causing issues20:45
daveshahOr possibly even a bad pin assignment on CS, so it's floating?20:45
tpbTitle: Unsee Free online private photos sharing (at
dmin7that is the whole "boot" .. so same size as before ~130k20:49
daveshahYep, that's the fpga booting up20:50
daveshahLooks like the processor never starts20:50
daveshahIs resetn going high as expected?20:50
daveshahI'm afraid that's all I can think of for tonight. Happy to help again tomorrow though20:54
dmin7i think it might be time for a break here also .. thx a lot!20:58
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