Tuesday, 2018-05-08

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shaprDoes yosys support PolarFire? I'd never heard of 'em before this RISC-V board15:32
daveshahshapr: no, but I suspect synthesis for polarfire wouldn't be too hard15:36
daveshahP&R and bitstream generation would be the hard part15:37
shaprthis board https://www.prnewswire.com/news-releases/microsemi-and-sifive-launch-hifive-unleashed-expansion-board-enabling-linux-software-and-firmware-developers-to-build-risc-v-pcs-for-the-first-time-300642936.html15:37
shaprthat's quite the url15:38
shaprand these FPGAs https://www.microsemi.com/product-directory/fpgas/3854-polarfire-fpgas15:38
shaprdaveshah: I have the newbie impression than PnR is the same for all FPGAs15:41
shaprtime to learn more15:42
shaproh wait, of course it would depend on the internal layout15:42
daveshahshapr: although it would be possible to write a generic place and route tool, there isn't really one out there in the same way that Yosys is a generic synthesis tool15:42
shaprI guess I thought that internal layout would be a parameter you hand to the PnR program?15:42
daveshahBut the only open tool that works like that is VPR, which is currently only for virtual, theoretical FPGAs15:42
daveshahBut there's a big effort to make it support real FPGAs like the ice40 and artix7 too15:43
shaprsilly question, is there a standard approach to PnR? I'd guess it uses binary decision diagrams internally?15:43
shapralthough I could think of other approaches, BDDs seem easiest15:44
awyglesimulated annealing is the traditional approach15:44
shaprhm, does that have issues with local minima?15:44
awygleSome yes but it's pretty good. The problem is it's slow.15:45
awygleOr at least, not very parallelizable15:45
ZipCPUISE has a *horrible* time dealing with (inoperable) local minima.15:45
shaprI think there are better approaches.15:46
awygleThere are a few other approaches. Analytic approaches are popular.15:46
shaprI was thinking about prolog-style constraint solving, but I bet that's not much better than simulated annealing, maybe less likely to get stuck in local minima15:47
awygleYou're in ##openfpga right? The wiki on github has a list of papers I collected on parallel place and route15:47
awygleAlso rqou tried to implement constraint solving for a CPLD and had issues15:47
shapraha https://github.com/azonenberg/openfpga/wiki/Place-and-Route-Research15:48
tpbTitle: Place and Route Research · azonenberg/openfpga Wiki · GitHub (at github.com)15:48
shaproh that sounds interesting15:48
shaprI think place and route is the same as a bunch of other things, I should really write up a blog post15:49
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awygleI'd be interested in seeing that15:50
awygleazonenberg has an idea about molecular dynamics algorithms for PnR15:50
shaprin the style of fold.it ?15:50
awygleIt's ultimately an energy minimization problem15:50
shaprright, but there are a bunch of approaches and I think they're almost all equivalent in function, but different in ease of implementation/execution15:51
shaprI think it's the same thing the homomorphic encryption projects use to optimize logic, same as SIMD Within a Register, and others15:51
awygleHuh, I see homomorphic encryption but SWAR doesn't jump out at me15:53
awygleRegardless, I'd love to see the blog15:53
awygleVery relevant to my interests obviously15:53
sorearPnR is interesting because it’s fundamentally geometrical, you need to minimize 2D wire lengths15:53
shaprglobal minimization of the sum of all wire lengths, with max wire length also minimized15:54
shaprthat's a really interesting problem15:54
daveshahyou also have to take into account timing paths15:55
awygleYeah it gets complicated once you add in timing constraints15:56
daveshahthere may be different number of blocks in different paths, so just looking at wirelength alone isn't ideal15:56
daveshahafaik this is why arachne-pnr fails in terms of timing15:56
awygleI find it weird that so many tools minimize total wire length. Max seems to be the obvious FoM (in the absence of timing info)15:56
daveshahyeah, I'd like to experiment with the FoM in arachne at some point15:57
shaprWhat's FoM?15:57
daveshahfigure of merit15:58
daveshahto be minimised15:58
shaprwould be fun to do a PhD on an FPGA tinkertoy kit15:58
shaprthere's too much cool stuff to learn, not enough time16:00
sorearYou need to at least constrain total because the chip has a finite amount of wire and routing resources16:00
awygleYeah but that's not really length either, that's density16:03
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rqouawygle, shapr: the current CPLD code is still technically formulated as "constraint solving"17:15
rqouit's not naively using a SMT solver anymore though17:15
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shaprprice is out for the improved risc-v board, I can't spare $2k after spending $1k on the risc-v board that hasn't arrived yet.17:58
shaprnow I wish I'd saved my money for this improved board :-(18:03
sorearAFAIK the new one is not useful if you don’t also have the old one18:05
awygledoes the new one have a polarfire on it?18:10
shaprawygle: https://www.crowdsupply.com/microsemi/hifive-unleashed-expansion-board18:11
tpbTitle: HiFive Unleashed Expansion Board | Crowd Supply (at www.crowdsupply.com)18:11
shaprthat's the new board18:11
awyglepolarfires are cool18:11
awyglelots of fast serdes18:11
shaprBut no yosys support?18:12
shaprI'm in that lucky position of only using FPGAs for fun, so I don't have to use closed source tools.18:12
shaprsorear: good point, I thought it was an entirely new board18:13
awygleno and not likely to be for a long time imo18:17
awyglemicrosemi being mostly military/space seems like the kind to get uptight about that kind of thing18:17
daveshahI heard on the grapevine all PolarFile bitstreams are encrypted (by default with a factory key)18:20
daveshahSo legal fuzzing (for people in DMCAland at least) may be simply impossible18:20
sorearI read the documentation and can confirm this18:21
daveshahI'm not sure if using your own key would help, if it's a standard algorithm and implementation18:23
daveshahI feel that messing too much with these things could result in a knock on the door...18:23
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awygleYeah I think technically if it says "it's aes256" and then you implement aes256, and RE the "program key" process but not the "extract key" process, you'd technically be legally OK, but only technically lol18:24
awygleI personally would not risk it18:25
daveshahGiven how many other FPGAs there are to play with, it's just not worth the risk indeed18:26
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sorearYou can supply a custom key; doing so and then REing the cipher (it ain’t aes-gcm) might work when I’m not in freedomland18:35
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sorearPCIe on Xilinx-7 with symbiflow will probably happen first18:39
daveshahOr ECP5...18:40
daveshahBut 7 series almost certainly first18:40
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daveshahYou could of course do PCIe on an ice40 with a PCI->PCIe bridge18:41
daveshahPCI on an ice40 should be manageable18:42
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shaprthat discussion makes me sad18:52
shaprthe DMCA makes me sad18:54
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ZipCPUshapr: Be glad you are funding open source FPGA design then!19:35
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shaprZipCPU: means I don't want to send in money for this expansion board20:02
shapralso, I corrupted the drive on my novena, gotta reinstall :-(20:03
ZipCPUSmile, it's good for you!  :D20:03
ZipCPUshapr: Have you seen my most recent video demo?20:03
shaprnope, link?20:03
tpbTitle: GitHub - ZipCPU/vgasim: A Video display simulator (at github.com)20:04
ZipCPUI added a memory reader to the video generator, so it can now display anything stored in memory.20:04
shaprwow, nifty20:04
ZipCPUWhile it's not implemented in an FPGA (yet), the code is ready for an FPGA as the next step.20:05
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