Thursday, 2018-05-03

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ZipCPUYaayy!!!  Got my first yosys patch accepted.  Yosys now suppoprts string literals containing \a, \f, \v, and (my favorite) \r.11:45
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qu1j0t3yeah, \r is kind of important.12:17
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daveshahZipCPU: congratulations :)12:44
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shaprI got the ice40 board for my novena, but I have no idea how to load a bitstream onto it.14:17
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cr1901_modernZipCPU: You've done Verilog simulation once or twice (or 5), right? :)15:25
ZipCPUYes.  All with Verilator though.15:27
ZipCPUshapr: What board?15:27
cr1901_modernWell, maybe you can explain what this code is doing?
cr1901_modernThe comment says: "This model samples io input signals 1ns before the SPI clock edge", but I don't see how that's possible15:28
tpbTitle: picorv32/spiflash.v at master · cliffordwolf/picorv32 · GitHub (at
tpbTitle: Novena iCE40 Add-On | Jamie Craig (at
ZipCPUcr1901_modern: Are you building a SPI (or QSPI) controller?15:28
* ZipCPU looks up shapr's board ..15:29
shaprafter reading some of the blog posts, I think maybe I need a bitstream loaded onto the xilinx chip to pass through pins or something?15:29
cr1901_modernZipCPU: Neither, I want to use this core to debug something. But I want to understand how it works too :)15:29
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ZipCPUshapr: Does that design even have a Xilinx chip?15:29
shaprThe novena has a ... 6 series ... spartan?15:30
cr1901_modernio0/1/2/3, when treated as inputs, will change at any time, typically after the previous clk edge.15:30
cr1901_modernI don't see how delaying by #1 ns will all of a sudden get you to "1 ns before the next SPI clock edge",15:30
ZipCPUHave you dug into what the flash is doing?15:31
cr1901_modernIf anything, it looks like the model "samples 1ns after the previous SPI clock edge", not 1ns _before_ the upcoming clk edge15:31
cr1901_modernZipCPU: Hmmm, I missed something (spi_action task), but Idk if it'll answer my q15:32
* ZipCPU pulls up novena's schematic ...15:33
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shaprI was hoping to have this working last night so I could do a lightning talk about it today, but instead I'm doing audience participation of bitcoin proof of work.15:34
ZipCPUThere are *two* FPGA's on that board?  Or do I have the wrong board .. ?15:34
shaprpretty sure there's only one15:34
tpbTitle: Novena | Crowd Supply (at
* ZipCPU must be looking at the wrong board ...15:35
shaprthis is the board:
tpbTitle: Novena Main Page - Studio Kousagi Wiki (at
shaprspartan-6 CSG32415:36
ZipCPUcr1901_modern: I've done all of my SPI testing with my own (verilator-based, c++) xSPI flash simulator.15:36
ZipCPUIt's full featured enough that I can boot my CPU off of it.15:36
knielsencr1901_modern: If you sample io0_delayed at the SPI clock edge, then you (effectively) sample io0 1 second before the clock edge15:36
knielsencr1901_modern: because io0_delayed is equal to the value io0 had 1 ns earlier15:37
shaprknielsen: oh, I use your floorplan viewer when I'm doing FPGA intro lightning talks, thanks for writing that.15:37
knielsen(but I didn't check in detail what the code is doing)15:37
knielsenshapr: glad if you found it useful!15:37
ZipCPUshapr: Ok, I see the S6 reference ... the board should've come with software to load it, or at least instructions on how to load it using Xilinx or some other tool ...15:38
cr1901_modernknielsen: Oh... ._.15:39
shaprZipCPU: I suspect this is "if you have to ask, shouldn't have ordered"15:40
cr1901_modernZipCPU, knielsen: thanks for both your help. I just didn't see it15:40
shaproh well, I'll figure it out.15:40
ZipCPUshapr: Not necessarily.  I've seen a lot of customers ask on the forums for well supported boards.  Most often the problem is that they just don't know where to look (yet) for what they need.15:40
shaprI think 50-80 of these boards were produced15:41
shaprah, 39 boards
tpbTitle: Novena Mezzanine Board (at
ZipCPUshapr: You need to use the "" script from the GPBB example code.15:41
shaproh, that's it?15:42
ZipCPUThat in itself also depends upon the devmem2 program.15:42
ZipCPUSee the instructions here:
tpbTitle: FPGA getting started - Studio Kousagi Wiki (at
ZipCPUJudging by the bottom of that page, it looks like you can also load bitstreams via OpenOCD over JTAG as well.15:43
shaprI need to send you money for consulting :-P15:44
shapriirc, your prices are quite reasonable15:44
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ZipCPUPerhaps we should negotiate off forum.15:45
shaprThree day music festival this weekend, if not this evening, then next week.15:46
shaprZipCPU: the blog posts about this board imply there isn't yet VHDL to forward the pins through the Xilinx chip15:47
shaprbut I could be wrong, I just don't know yet15:47
ZipCPUDon't know ... haven't read them.15:50
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mattvennquick question about doing maths with fpga17:48
mattvennin c, if I have a register that's a byte in length, and some arithmetic operation happens that overflows it17:49
mattvennthen the maths happens correctly, and I get left with the part that fits in the reg17:49
mattvennbut in an fpga, say I'm doing some maths with some different width registers,17:49
mattvennhow do I make sure that there is enough space for the operation to happen correctly?17:50
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mattvenn       8 bit    10bit  10bit        2bit       parameter=19       4bit     parameter=1617:54
mattvennassign y_img = (y_px - y_numbers - (addr_rom * height_numbers)) + number * height_numbers;17:55
tpbTitle: Bit growth in FPGA arithmetic (at
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