Wednesday, 2018-04-25

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mithroZipCPU: it gets optimised down to 6 LUTs if I understand correctly...01:49
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daveshahmithro: putting `(* keep *)` on all the submodules should work06:37
daveshahOtherwise, I think there's a way of running abc on the submodules rather than the flattened design, by running hierarchy after abc06:38
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mithrodaveshah: Well, ideally I would like a design which /can't/ be optimized away14:59
mithrodaveshah: I feel like maybe you could use a SAT solver to fill in the LUT init pattern to make sure?14:59
ZipCPUThat was what the reddit/yosys article discussed, "Keep duplicate FF through Opt_merge".  Clifford demonstrated in the response that you could keep ABC from optimizing sections of your design via the (* keep_hierarchy *) attribute.15:00
mithroZipCPU: Yeah - knew about the keep stuff - but I was more looking for something that can't be optimized away...15:03
daveshahThat design will always be optimised unless the optimiser is broken15:04
daveshahNo SAT solver will help with that15:04
daveshahEither you need more inputs or a keep command15:04
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mithrodaveshah:  Out of interest how would you "prove" that?15:05
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daveshahNot sure TBH15:05
daveshahActually, I was thinking about an arch with muxes. Too much ECP5 stuff15:06
daveshahMaybe there is a pattern that works15:06
mithrodaveshah: Well, I guess you have "existence proof" -- IE ABC was able to optimize it so, therefore... :-P15:06
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daveshahI think this is a proof that a 6-input combinational network will produce no more than 6 LUT4s after optimisation: A 6-LUT can always be built from 4 4-LUTs and a MUX4. Proof by Yosys that a MUX4 can be built using only 2 LUT4s. Hence 6 LUT4s in total15:16
daveshahFeel free to point out a flaw in this15:17
cr1901_modern4 4-LUTs (I can visualize a MUX4 from 2 4-LUTs just fine)?15:21
cr1901_modernBasically, I don't see how you get 6 bits of arbitrary functions from 4-LUTs and a MUX15:24
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cr1901_modernWait nevermind. I can visualize a 5-LUT from 2 4-LUTs and a 2-MUX, so 6-LUT is just an extension of that (too lazy to actually do it in my head tho :P)15:26
sorearwhat does the MUX4 from LUT4 look like?15:28
soreari couldn't figure out how to do it with less than 3 myself15:28
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photonany recommendation for a sequence of abc command to minimize the area?15:33
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ZipCPUDoesn't the "opt" yosys command do that?15:35
photonwell, opt does not do a great job15:39
ZipCPUIf there's another means of doing so, I'd like to find it.  I've got some code I'd like optimized better .. ;)15:40
photonfor a test design design compiler gave 160 gates and yosys/abc gave 1000 gates!15:40
awygleare you also running "abc"?15:40
photonI played abit with abc commands to reduce the number to 600 gates15:40
photonbut, it is still far away from 160 gates15:41
photonreported by DC15:41
ZipCPU"gates" or "LUT"s?15:41
photonI am mapping the design to ASIC standrd cell library15:42
ZipCPUDoes your design have RAM elements within it?15:42
photonif they do good job for ASIC they should for FPGA15:42
photonit is a pure combinational design given as a set of boolean equations15:43
cr1901_modernsorear: Gonna have to take a rain check on that one. My mental picture was wrong. But I imagine it can be done15:47
sorearcr1901_modern: i'm asking daveshah not (necessarily) you15:48
cr1901_modernsorear: Oh sorry, I made it all about me :P15:48
sorearyou can answer it if you want, but I don't expect you to know details of daveshah's 2-LUT MUX415:49
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daveshahThis was done using Yosys's `synth_ice40` and `show` commands15:52
daveshahIt's a beautifully tricky solution15:54
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cr1901_modernOh, I almost got it right (forgot to feed in 1:1-0:0 to the _first_ 4-LUT as well as the second)15:56
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sorearthat is amazing16:03
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daveshahNB - in Yosys notation y:x - b:a maps bits y..x to bits b..a - so 1:1-0:0 means select bit 1, for example16:09
daveshahIt's a bit of an odd notation, but it's also flexible16:09
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shaprThe ice40 boards for my novena shipped from austria, that'll be fun.17:29
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emebice40 in a novena? doesn't novena already have an FPGA in it?20:35
sorearYes but it’s not usable with FOSS20:37
tpbTitle: Novena iCE40 Add-On | Jamie Craig (at
emebYeah - not being able to run the Spartan tools on the Novena is a PITA.21:00
emebI built a little RPi "hat" with an Ultra-Plus on it and it's fun to build the bitstream right on the RPi.21:01
emebEven works on an RPi Zero.21:01
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