Thursday, 2018-04-05

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philtorZipCPU, did you do a writeup on this HITL testing methodology? That would be an interesting read.01:03
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ZipCPUphiltor: Not specifically, but I think I might have mentioned it in the FFT article,01:35
ZipCPU... let me check ...01:45
philtorIt would make a great blog post :)01:48
tpbTitle: FFT debugging (at
ZipCPUYeah, so ... you can read the post if you like, or I can tell you the story ... :)01:53
ZipCPUThe story goes back to a dark man, with a dark purpose, waiting on a dark night ... Oops, sorry, that's Aladdin ... let me try again ...01:54
ZipCPUNo, seriously, I was programming my very first FPGA.  The hardware engineer had delivered me a circuit board.  The Linux engineer had placed a Linux distro on the ARM chip on that board.  The FPGA was connected via an auxiliary bus to the ARM chip.01:55
ZipCPUThe hardware engineer who had "proved" that the board worked, gave it to me empty with only one configuration on it--one that allowed the reading from or writing to bus addresses.01:56
ZipCPUHence, from the Linux program I could read from a memory-mapped address within the FPGA.01:56
ZipCPUMy first program mapped a 3-bit input from an offset A/D into a 4'bit value that would properly handle the task.  I tested it via writing the value to the bus, and reading the result back off.01:57
ZipCPUI managed to use that same basic interface to build a GPS front-end processing system, and again to build a custom radio system.01:58
ZipCPUThe custom radio was fascinating, since I would write to a "clock register" that would step the entire design.  I could then come back and read information back off at my convenience, one word per clock.01:58
ZipCPUI'd write the "input" from the antenna (i.e. simulation) into one register, and then watch as it cascaded through the processing chain.01:59
ZipCPUOn the whole, I found the technique quite useful at the time.01:59
ZipCPUIn hind sight, I might've moved through the project faster if I had used simuation--since it would take ISE (Spartan 3) about 15 minutes to build each test design, and I can often simulate something in less than a minute or two.02:00
ZipCPUWhen I had to stop stepping the design, it was as easy as setting that step register field to a 1'b1, and all the debugging code would be optimized out of the design.02:01
ZipCPUWhen I switched to full speed, I had two problems.  The first I solved with the predecessor of the wishbone scope, creating something like a chipscope capability.  The other was the fact that ... my simulated radio matched the receiver clock perfectly.  Oops.  Reality was a touch more difficult.02:02
ZipCPUThe funny part was the response of the veteran FPGA designers watching me with my first design.  In general, they just shook their heads in dismay.  When I delivered, they then scratched their heads somewhat.  Either way, the approach was an anomaly.02:03
ZipCPUphiltor: That's the basic story.02:04
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keesjZipCPU: I now better uderstand why you asked about my serial to register mapping project.05:25
keesjI never user chipscope so far (i remember scanning some jtag scan chain but somewhere I must have run into problems) This was on a Digilen Basys2 Xilinx Spartan-3E FPGA.05:28
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promach__for the smt_step, how do I reference it in assert() ?16:25
ZipCPUpromach__: Give me a little more back ground ... what are you talking about?16:28
promach__ZipCPU: I am trying to assert a relationship between 'cnt' and 'state' as in
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ZipCPUAh ... to my knowledge, you don't reference the smt_step number in an assertion.  You can create your own counter to reference if you would like, but you can't reference that one.16:32
promach__ok, I see. Thanks16:32
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