Monday, 2018-04-02

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ZipCPUkeesj: You've been trying to build an FPGA command and control link via a serial port, right?19:19
ZipCPUHaving any success?19:23
keesjWell. I decided I was going to use wishbone today hence will first try that approach19:25
keesjI think the solution will be nicer if i write the glue logic in a soft cpu (serial->cpu<-can_controller)19:26
ZipCPUGot enough wishbone information to get yourself going?19:27
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keesjWell. I did a similar project (on SPI triggers) before but this is from scratch :P19:33
ZipCPUYou were posting in the VHDL channel.  What brings you to yosys, since yosys is primarily a verilog tool?19:34
keesjBut this is my first time on this channel (I have been active on ##vhdl)19:34
keesjopen source , open hardware and anticipation off and
tpbTitle: TinyFPGA BX | Crowd Supply (at
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ZipCPUI've got most of my TinyFPGA design done ... just still need to prove that the flash controller I just built works as designed.19:36
keesjare you working on that?19:37
ZipCPUI'm not employed working for the TinyFPGA team.19:38
keesjAnyway at FOSDEM I also saw some nice projects around yosys hence .. I will need to investigate this later. First .. make my project work19:39
ZipCPUOk, sure, welcome to the channel!19:39
ZipCPU<shameless plug> Feel free to browse the ZipCPU blog as well, at </shameless plug> :)19:39
keesj:p (currently using the papilio  pro and the zpuino soft core)19:41
ZipCPUSure.  A tiny zpuino core makes a lot of sense for an iCE40 design.19:41
keesjI have read your website before nice to meet on IRC19:51
ZipCPUThat's me!19:51
ZipCPUBeen trying to formally verify the ZipCPU today, and so far I've been *quite* successful!19:52
keesj also sounds very interesting20:00
tpbTitle: GitHub - cliffordwolf/picorv32: PicoRV32 - A Size-Optimized RISC-V CPU (at
ZipCPUYes, it is quite interesting.  I've looked over it myself, although I've never tried it.20:00
keesjI only listened to it on the amp hour podcast (374)20:01
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