Thursday, 2018-03-29

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dmin7hi, i wonder, has anyone ever done anything with icosoc raspi interface besides using it to write debug output? (reading data from it eg x)08:45
dmin7or the SPI that is used for flashing from within C code ..09:01
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ZipCPUYes, dmin7, I've built the parallel port into a full bidirectional interface with a TCP/IP redirect09:26
dmin7oh, nice .. is there some code i can look at?09:30
ZipCPUIt's in
tpbTitle: GitHub - ZipCPU/icozip: A ZipCPU demonstration port for the icoboard (at
ZipCPUThere's several parts to the interface.  The FPGA side is kept in rtl/pport IIRC09:42
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ZipCPUThe pport->TCP/IP bounce takes place in  sw/host/netpport09:43
ZipCPUPrograms using the interface would look something like the sw/host/wbregs program, and follow the interface in sw/host/devbus.h09:44
dmin7i was affraid you were gonna say that (: .. i'm (still) using the picorv32/icosoc setup .. and as far as i can see your icozip doesn't have much to do with "icosoc"?09:46
xerpishouldn't typedefs be allowed outside of modules?09:50
xerpisyntax error, unexpected TOK_TYPEDEF, expecting TOK_LOCALPARAM or TOK_ENDPACKAGE09:50
xerpiI have a typedef inside a package and outside of a module09:50
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ZipCPUdmin7: Ahh, I'm sorry, I missed that part of your question.  :(09:52
ZipCPUxerpi: In Verilog?  Does yosys even support that?09:53
xerpiZipCPU, SystemVerilog09:53
ZipCPUI didn't think yosys had full sV support (yet) ...09:54
xerpifrom the SystemVerilog standard "Types, nets, variables, tasks, functions, sequences, properties, and09:54
xerpicheckers may be declared within a package. "09:54
xerpipage 73809:54
xerpiZipCPU, yeah right09:55
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ZipCPUWell .. the front end does recognize the token, so ... there's at least something there ...09:55
xerpiI guess Verilog only allowed typedef inside of modules09:58
dmin7ZipCPU: do you happen to have some instructions on howto get ICOZIP running (i'm using the icezero, not the icoboard, so i would have to adjust the pinout at least, i guess)10:02
ZipCPUSadly, no.  I spent so  much time getting the pport interface to work, that I never managed to get the CPU up and running.10:04
ZipCPUChief among the things to be done was the SRAM--I never managed to build the interface to it, or verify the code that uses that interface in simulation10:05
ZipCPUThe SPI might need some work as well, and then the software "demos"10:06
dmin7oh, ok, i guess i'll just try to get some sort of SPI working between the pi and icosoc then10:11
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xerpiis this a verilator bug or the standard?11:14
xerpibar1 and bar2 have different values11:14
xerpithat's the full code:
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ZipCPUxerpi: Have you looked through the code Verilator creates??11:38
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ZipCPUAnyone interested in voting on the logo contest at:
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mjo-uk_s/our toosl/our tools/19:56
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