Friday, 2018-03-23

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ZipCPUnikhilp: Please stick around next time, we like to chat but ... sometimes you need to wait a while for a response.11:28
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philtorSo there's a bridge between GHDL and Yosys now?19:31
tpbTitle: GitHub - tgingold/ghdlsynth-beta: VHDL synthesis (based on ghdl) (at
philtora VHDL frontend?19:33
philtorrequires a patch to yosys source19:34
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ZipCPUphiltor: I know there's a vhdl2verilog front end to yosys, I just don't know how well it works19:37
philtorThis ghdlsynth looks like it would be a better path - GHDL's VHDL parser is pretty mature19:37
philtorObviously, it's very beta at this point19:38
philtorHowever, it requires patching yosys source and likely the source has gotten out of sync with that patch by now19:39
awygleYes, that's very exciting19:39
philtorThe patch is fairly small, though.19:39
* ZipCPU just doesn't get all that excited about VHDL tools ... ;P19:39
awygleGHDL is GPL though, as pointed out on another channel. I wonder how that works.19:39
philtortgingold should do a pull request to YosysHQ for that patch19:40
awygleZipCPU: I'm excited for someone to give me a reason to learn VHDL!19:40
ZipCPURun away!19:40
daveshahIt looks like it can also be loaded as a dynamic library without needing a patch19:40
daveshahBut I haven't investigated much19:40
philtorYes, but a patch is requireed to support that19:40
philtorso I don't think licensing should be an issue19:41
philtorIn fact, the patch appears to only be to the yosys Makefile19:41
philtoryes, that seems to be the only thing being patched.19:42
philtorGood separation between the two projects19:42
philtorno licencing issues19:42
philtorlooks a lot like the verific bridge19:43
philtorPretty cool, but needs work.19:44
philtorFortunately, the only code in the bridge is in C++19:44
philtorso you don't need to learn Ada19:44
philtorto contribute19:44
daveshahLooks like the dynamic library does work without the patch using the Yosys module system - but I agree the patch is a much nicer approach19:45
daveshahAFAIK a lot of the work is being done by the `synth` part of ghdl which is in Ada, I don't know how complete that bit is19:46
tpbTitle: ghdl/src/synth at master · ghdl/ghdl · GitHub (at
philtorah, right. It's actually in the GHDL codebase already.20:04
* shapr hops cheerfully20:07
shaprvacation is GREAT!20:07
ZipCPUAt the last robotics competition, they asked what a robot's favorite type of music.  The FROGbots team replied "Hip hop", although the answer for all the other robots was "Heavy metal"20:10
shaprZipCPU: twitter worthy for sure20:11
ZipCPUHere's a question for those with experience using the concurrent assertions that yosys (without verific) doesn't (yet) support ...20:51
ZipCPUWhat's the "killer app" that makes such assertions valuable?20:51
ZipCPUWhat's the "killer app" that makes such *concurrent* assertions valuable?21:01
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ZipCPUHmm ... assertions for a UART: 117 lines without concurrent assertions, 47 lines with ...21:57
ZipCPU... wonder what the difference would be for a SPI flash ... ?21:58
sorearcan concurrent assertions always be replaced with regular assertions?22:02
awygleZipCPU: all i want in the world is for a notion of a "property" as a first class object22:02
ZipCPUsorear: I think the right way to answer your question would be to start with: there are two types of assertions (or assumptions) concurrent and immediate.22:03
ZipCPUyosys currently only supports the immediate assumptions.22:03
ZipCPUconcurrent assumptions include the System Verilog sequence/property language subset.22:04
cr1901_modern? "assert property" is a concurrent assertion.22:04
cr1901_modernyosys supports that, it just doesn't support anything else :P22:04
awygleyosys only supports that in a trivial way, and does so by converting it to the implied immediate version, iirc22:04
cr1901_modern slide 11, awygle is correct. And I even read this presentation multiple times :(22:07
ZipCPUcr1901_modern: Yosys does not support: assert property (A |-> B ##1 C [*3:8] ##1 !B); as an example.22:08
* awygle prints out "awygle is correct", frames it, adds it to a wall of dozens of similar frames22:08
cr1901_modernWell idk if yosys supports ##, but it certainly doesn't support |->22:08
cr1901_modernlast I checked*22:09
awyglei just want to be able to do "assert property(acks_are_happy)" and define what happiness means to acks somewhere else22:09
* ZipCPU signs awygle's printout22:09
cr1901_modernAlso, obligatory link. Have fun!
tpbTitle: system verilog - SystemVerilog: implies operator vs. |-> - Stack Overflow (at
awygleotherwise it feels like an SLA principle violation22:10
awyglebut it's possible i could solve this problem with functions if i knew verilog better22:10
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