Saturday, 2018-03-10

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ZipCPUSo ... I spent today trying to understand system verilog's concurrent assertion language.02:18
ZipCPUNow I think Clifford gave us a gift by *not* including it in yosys.02:18
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awygleZipCPU: oh? do tell04:07
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tpbTitle: gist:6ae69cc05e13e412d0389d11685f7a70 ยท GitHub (at
ZipCPUawygle: Those are some wishbone bus properties in the concurrent assertion subset of System Verilog.15:02
ZipCPUWhile I like the language for its expressive ability, it's ... not nearly as easy to read and comprehend.15:02
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cr1901_modernawygle: You read this and reconsider your life choices
tpbTitle: SystemVerilog Assertions Tutorial (at
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cr1901_modernOh right this was the other reference I used:
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ZipCPUcr1901_modern: Yeah, I was referencing that tutorial a *lot* yesterday.18:34
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