Friday, 2018-03-09

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ZipCPUHey, this is cool!  Building an RGMII network interface.  Last time I did this, I had to iterate over many painful rounds with the simulator.  This time, I think I got it right with less than one bug found in the network code.04:12
ZipCPU(Other bugs were found in the bus addressing, etc.)04:13
ZipCPUThe difference?  This time I formally proved all of th network sub-components: add a CRC, add a hardware MAC, add a preamble, insure a minimum packet length, and then the inverse on the receive.04:13
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awygleZipCPU: nice!04:29
ZipCPU;)  The last time it was an RMII interface, but still ... I had to rebuild the whole thing to operate on 8-bits at a time instead of 4.04:29
awyglemy actual job has been throttled to 11, i look forward to getting back to personal projects...04:31
awyglei think i've come up with a way to prove the fifo that i find aesthetically superior to breaking out the internal pointers04:32
ZipCPUYeah, I understand comppletely about the job.04:33
ZipCPUAs for the FIFO, I'd love to see it ... but I'll be glad to wait until you either get it working or get stuck.04:33
awyglei'll be sure to show you when i get there :)04:33
awygleit may be somewhat ridiculous to stress out over these kinds of things, but i'm much more interested in developing an approach than a formally verified fifo in particular04:34
awyglecan you share anything about the project which has you developing an RGMII core?04:38
ZipCPUSure!  Most of the code is on line at although I haven't yet checked in all of the ethernet components.04:40
tpbTitle: GitHub - ZipCPU/videozip: A ZipCPU SoC for the Nexys Video board supporting video functionality (at
ZipCPUThe ethernet components themselves are coming from my OpenArty project, at
tpbTitle: GitHub - ZipCPU/openarty: An Open Source configuration of the Arty platform (at
ZipCPUOnly thing is .... they need to be modified from RMII to RGMII, and  I took the opportunity to add formal proofs along the way.04:42
ZipCPU(To be posted ...)04:42
awyglevery interesting! thanks04:44
awygle(this bot is kind of weird thoughj)04:44
ZipCPUYeah .... not sure I like it.04:44
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mattvenn_I got my i2c master workiong with the new sensor08:57
mattvenn_I made 3 changes: repeated starts, more setup/hold time consideration and learnt something new that was really important08:58
mattvenn_master shoudl nack the slave on the last data packet when reading08:58
mattvenn_it's in the spec but it hadn't mattered on previous sensors. This one actually followed the spec and kept the sda line down without the final nack from the master08:59
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mattvenn_this is a useful guide to the spec:
mattvenn_and this one has very clear pictures to show who should control SDA when:
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ZipCPUmattvenn_: I2C master for an iCE40?  How many LUT4's?12:31
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ZipCPUAhh, ok, got it ... my I2C master must need some serious work then.12:54
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mattvenn_mine still doesn't handle nacks from slaves or clock stretching13:02
ZipCPUOh, well ... that is a difference.  Mine handles both.  How does yours handle losing a bus arbitration battle?13:15
mattvenn_single master only13:16
mattvenn_to this day I've still never used a multimaster i2c bus13:16
ZipCPUWell, .. there's another difference then.  You consider that you *own* the bus.  Must make things nice.  ;)13:16
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awygleI recommend avoiding multi master I2C if at all possible16:12
ZipCPUawygle: Yeah, sure, but ... it's the protocol.16:13
awygleSure, and sometimes you can't avoid it. But it's a bad protocol, and sometimes you can :-P16:21
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mattvenn_take a look at page 8 of
mattvenn_useful table for what is required for fulfilling different parts of the spec16:36
mattvenn_my module supports all mandatory requirements of single master16:37
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