Thursday, 2019-05-02

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hackerfooHi, I'm working on modeling the Xilinx 7-series, and I want to model two chained muxes, but it seems that this isn't currently possible.18:31
* hackerfoo posted a file: Screenshot from 2019-05-02 11-14-47.png (96KB) < >18:32
hackerfooI flattened the two muxes, but there's no way to tie two muxes together, and no support for muxing buses.18:34
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