Monday, 2019-05-13

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acomodikem_: Hi, I have created a PR with an implementation of equivalent tiles
tpbTitle: WIP [DNM]: Equivalent Tiles placement by acomodi · Pull Request #559 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
acomodikem_: It currently fails on CI as there the PR also moves the top level pb_types-only tags to the tiles tags (which are not present in the current test architectures)13:38
acomodikem_: can you have a look at it and give me feedback when you have some time, please?13:42
acomodikem_ : I have tested it within the symbiflow environment and it correctly places clustered blocks in equivalent tiles and VTR produces valid outputs that do work on HW13:43
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tpbTitle: Placement delta delay block choice seems limited · Issue #563 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
litghostkem_: Should generate an error on non-finite delay values?21:44
tpbTitle: vtr-verilog-to-routing/place.cpp at master · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
litghostkem_: It tests for < 0, but I have a case where it generated "inf"21:44
litghostkem_: And it's for blocks that definitely have connectivity21:44

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