Tuesday, 2019-05-07

*** tpb has joined #vtr-dev00:00
litghostkem_: I have a question about IPIN and OPIN rr nodes and IPIN -> SINK and SOURCE -> OPIN edges22:40
litghostkem_: Is it legal to have IPIN nodes with capacitance?  And can the IPIN -> SINK/SOURCE -> OPIN edges not be vpr_delayless_switches?22:41
litghostkem_: Check route will explode (https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/src/route/check_rr_graph.cpp#L468), but is that because the rrgraph builder never does it, or because the routing algo expects IPIN/OPIN nodes to have no capacitance?22:44
tpbTitle: vtr-verilog-to-routing/check_rr_graph.cpp at master · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)22:45

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